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Datasheet Microchip SY10E151

ManufacturerMicrochip
SeriesSY10E151

The SY10/100E151 offer 6 edge-triggered, high-speed, master-slave D-type flip-flops with differential outputs, designed for use in new, high-performance ECL systems

Datasheets

  • Download » Datasheet PDF, 92 Kb, File published: Nov 17, 2016
    SY10/100E151 - 6-Bit D Register
    Docket ↓
    NOT RECOMMENDED FOR NEW DESIGNS
    SY10E151
    SY100E151 6-BIT D
    REGISTER Micrel, Inc. SY10E151
    SY100E151 DESCRIPTION FEATURES
    в–  1100MHz toggle frequency
    ■ Extended 100E VEE range of –4.2V to –5.46V The SY10/100E151 offer 6 edge-triggered, high-speed,
    master-slave D-type flip-flops with differential outputs,
    designed for use in new, high-performance ECL systems.
    The two external clock signals (CLK1, CLK2) are gated
    through a logical OR operation before use as clocking
    control for the flip-flops. Data is clocked into the flip-flops
    on the rising edge of either CLK1 or CLK2 (or both). When
    both CLK1 and CLK2 are at a logic LOW, data enters the
    master and is transferred to the slave when either CLK1 or
    CLK2 (or both) go HIGH.
    The MR (Master Reset) signal operates asynchronously
    to make all Q outputs go to a logic LOW. в– 
    в– 
    в– 
    в–  Differential outputs
    Asynchronous Master Reset
    Dual clocks ...

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Other Options

SY100E151

Manufacturer's Classification

  • Clock and Timing > Clock and Data Distribution > Flip Flops, Registers

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