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Datasheet Microchip SY100E167

ManufacturerMicrochip
SeriesSY100E167

The SY10/100E167 offers six 2:1 multiplexers followed by D flip-flops with single-ended outputs, designed for use in new, high-performance ECL systems

Datasheets

  • Download » Datasheet, PDF, 160 Kb, 11-11-2015
    SY10/100E167 - 6-BIT 2:1 MUX Register
    Docket ↓
    SY10E167
    SY100E167 SY10E167
    SY100E167 6-BIT 2:1 MUX-REGISTER SYNERGY SEMICONDUCTOR FEATURES The SY10/100E167 offer six 2:1 multiplexers followed
    by D flip-flops with single-ended outputs, designed for use
    in new, high-performance ECL systems. The Select (SEL)
    control allows one of the two data inputs to the multiplexer
    to pass through. The two external clock signals (CLK1,
    CLK2) are gated through a logical OR operation before use
    as control for the six flip-flops. The selected data are
    transferred to the flip-flops on the rising edge of CLK1 or
    CLK2 (or both).
    The multiplexer operation is controlled by the Select
    (SEL) signal which selects one of the two bits of input data
    at each mux to be passed through.
    When a logic HIGH is applied to the Master Reset (MR)
    signal, it operates asychronously to take all outputs Q to a
    logic LOW. BLOCK DIAGRAM MUX
    D0b Q D SEL Q0 D5a D0a PIN CONFIGURATION
    D3b
    D3a
    NC
    VCCO в– 
    в–  ...

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SY10E167

Manufacturer's Classification

  • Clock and Timing > Clock and Data Distribution > Flip Flops, Registers

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