NOT RECOMMENDED FOR NEW DESIGNS
Micrel, Inc. JK FLIP-FLOP FEATURES
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SY100EL35
SY10EL35 SY100EL35 DESCRIPTION 525ps propagation delay
2.2GHz toggle frequency
High bandwidth output transistions
Internal 75KΩ input pull-down resistors
Available in 8-pin SOIC package The SY10/100EL35 are high-speed JK Flip-Flops. The
J/K data enters the master portion of the flip-flop when
the clock is LOW and is transferred to the slave and,
thus, the outputs, upon a positive transition of the clock.
The reset pin is asynchronous and is activated with a
logic HIGH. TRUTH TABLE(1)
J K R CLK Qn+1 L L L Z Qn L H L Z L H L L Z H H H L Z Qn X X H X L NOTE:
1. Z = LOW-to-HIGH transition. M9999-121205
hbwhelp@micrel.com or (408) 955-1690 Rev.: G 1
1 Amendment: /0 Issue Date: December 2005 SY10EL35
SY100EL35 Micrel, Inc. PACKAGE/ORDERING INFORMATION Ordering Information(1) …
