Datasheet Texas Instruments CDCVF2509PWG4
| Manufacturer | Texas Instruments |
| Series | CDCVF2509 |
| Part Number | CDCVF2509PWG4 |
3.3-V Phase-Lock Loop Clock Driver 24-TSSOP 0 to 85
Datasheets
CDCVF2509: 3.3-V Phase-Lock Loop Clock Driver datasheet
PDF, 742 Kb, Revision: D, File published: Feb 5, 2010
Extract from the document
Prices
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes |
Packaging
| Pin | 24 |
| Package Type | PW |
| Industry STD Term | TSSOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 60 |
| Carrier | TUBE |
| Device Marking | CKV2509 |
| Width (mm) | 4.4 |
| Length (mm) | 7.8 |
| Thickness (mm) | 1 |
| Pitch (mm) | .65 |
| Max Height (mm) | 1.2 |
| Mechanical Data | Download |
Parametrics
| Absolute Jitter (Peak-to-Peak Cycle or Period Jitter) | 50 ps |
| Function | SDR |
| Number of Outputs | 9 |
| Operating Frequency Range(Max) | 175 MHz |
| Operating Frequency Range(Min) | 50 MHz |
| Operating Temperature Range | 0 to 85 C |
| Output Drive | 12 mA |
| Package Group | TSSOP |
| Package Size: mm2:W x L | 24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP) PKG |
| Rating | Catalog |
| VCC | 3.3 V |
| t(phase error) | 125 ps |
| tsk(o) | 100 ps |
Eco Plan
| RoHS | Compliant |
Application Notes
- Generating Early Clock using TI's CDCVF2509/CDCVF2510 PLLsPDF, 68 Kb, File published: Jul 23, 2004
Model Line
Series: CDCVF2509 (4)
- CDCVF2509PW CDCVF2509PWG4 CDCVF2509PWR CDCVF2509PWRG4
Manufacturer's Classification
- Semiconductors > Clock and Timing > Memory Interface Clocks and Registers
