Datasheet Texas Instruments SN74SSQEC32882ZALR
| Manufacturer | Texas Instruments |
| Series | SN74SSQEC32882 |
| Part Number | SN74SSQEC32882ZALR |
JEDEC SSTE32882 Compliant Low Power 28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA 0 to 85
Datasheets
DDR3 Register and PLL datasheet
PDF, 700 Kb, File published: Aug 24, 2011
Extract from the document
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
Packaging
| Pin | 176 |
| Package Type | ZAL |
| Industry STD Term | NFBGA |
| JEDEC Code | S-PBGA-N |
| Package QTY | 2000 |
| Carrier | LARGE T&R |
| Device Marking | EC32882S |
| Width (mm) | 8 |
| Length (mm) | 13.5 |
| Thickness (mm) | .77 |
| Pitch (mm) | .65 |
| Max Height (mm) | 1.2 |
| Mechanical Data | Download |
Parametrics
| Absolute Jitter (Peak-to-Peak Cycle or Period Jitter) | 30 ps |
| Function | DDR3 Register |
| Number of Outputs | 60 |
| Operating Frequency Range(Max) | 945 MHz |
| Operating Frequency Range(Min) | 300 MHz |
| Operating Temperature Range | 0 to 85 C |
| Output Drive | N/A mA |
| Package Group | NFBGA |
| Package Size: mm2:W x L | 176NFBGA: 108 mm2: 8 x 13.5(NFBGA) PKG |
| Rating | Catalog |
| VCC | 1.35 V |
| t(phase error) | N/A ps |
| tsk(o) | N/A ps |
Eco Plan
| RoHS | Compliant |
Model Line
Series: SN74SSQEC32882 (1)
- SN74SSQEC32882ZALR
Manufacturer's Classification
- Semiconductors > Clock and Timing > Memory Interface Clocks and Registers