Datasheet Texas Instruments SN74SSTEB32866ZWLR
| Manufacturer | Texas Instruments |
| Series | SN74SSTEB32866 |
| Part Number | SN74SSTEB32866ZWLR |
1.5V/1.8V 25-Bit Configurable Registered Buffer With Address-Parity Test 96-BGA -40 to 85
Datasheets
25-Bit Configurable Registered Buffer w/Address-Parity Test datasheet
PDF, 1.9 Mb, File published: Apr 21, 2009
Extract from the document
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes |
Packaging
| Pin | 96 |
| Package Type | ZWL |
| Industry STD Term | BGA |
| JEDEC Code | R-PBGA-N |
| Package QTY | 1000 |
| Carrier | LARGE T&R |
| Device Marking | SEB866 |
| Width (mm) | 5.5 |
| Length (mm) | 13.5 |
| Thickness (mm) | .89 |
| Pitch (mm) | .8 |
| Max Height (mm) | 1.3 |
| Mechanical Data | Download |
Parametrics
| Absolute Jitter (Peak-to-Peak Cycle or Period Jitter) | N/A ps |
| Function | DDR2 Register |
| Number of Outputs | 25 |
| Operating Frequency Range(Max) | 410 MHz |
| Operating Temperature Range | -40 to 85 C |
| Output Drive | 8 mA |
| Package Group | BGA |
| Package Size: mm2:W x L | 96BGA: 74 mm2: 5.5 x 13.5(BGA) PKG |
| Rating | Catalog |
| VCC | 1.5,1.8 V |
| t(phase error) | N/A ps |
| tsk(o) | N/A ps |
Eco Plan
| RoHS | Compliant |
Application Notes
- DDR2 Memory Interface Clocks and Registers - OverviewPDF, 308 Kb, File published: Mar 25, 2009
This application report gives an overview of the existing JEDEC DDR2 Register and PLL Buffer specifications and compliant TI devices.
Model Line
Series: SN74SSTEB32866 (1)
- SN74SSTEB32866ZWLR
Manufacturer's Classification
- Semiconductors > Clock and Timing > Memory Interface Clocks and Registers