Datasheet Analog Devices HMC794LP3ETR

HMC794LP3E
v01.0612 Frequency Dividers & Detectors -SMT 2 GHz LOW NOISE PROGRAMMABLE
DIVIDER (N = 1 to 4)
Typical Applications Features The HMC794LP3E is ideal for: Low Noise Floor: -163 dBc/Hz at 10 MHz offset
and -160 dBc/Hz at 100 kHz offset • LO Generation with Low Noise Floor Programmable Frequency Divider, N = 1, 2, 3 or 4 • Clock Generators 200 MHz to 2 GHz Input Frequency Range • Mixer LO Drive 50% Duty Cycle Outputs • Military Applications Up to +10 dBm Output Power • Test Equipment Sleep Mode: Consumes 5 dBm -2 3 10 dBm Programmable in 2 steps
(see the Pout plots for each division ratio) -3 10 12 dBm Divider Output Characteristics
Differential Output Power
SSB Phase Noise @ 10 MHz Offset
SSB Phase Noise @ 100 kHz Offset +5 dBm Input Power, 2 GHz Input SSB Phase Noise @ 10 kHz Offset
Duty Cycle for Differential Mode +5 dBm Input Power -163 dBc/Hz -160 dBc/Hz -153 dBc/Hz 50 ±3 % Logic Inputs 1 VIH Input High Voltage 3 5 V VIL Input Low Voltage 0 0.4 V Information furnished by Analog Devices is believed to be accurate and reliable. However, no
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