Datasheet DS18B20 - 8
| Description | Programmable Resolution1-Wire Digital Thermometer |
| Pages / Page | 20 / 8 — 64-BIT Lasered ROM code. Memory. SCRATCHPAD. (POWER-UP STATE). EEPROM |
| File Format / Size | PDF / 496 Kb |
| Document Language | English |
64-BIT Lasered ROM code. Memory. SCRATCHPAD. (POWER-UP STATE). EEPROM
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link to page 8 link to page 8 link to page 9 link to page 10 link to page 8 link to page 8 link to page 11 link to page 9 link to page 9 link to page 9 DS18B20 Programmable Resolution 1-Wire Digital Thermometer
64-BIT Lasered ROM code
ter data, which is explained in detail in the Configuration Each DS18B20 contains a unique 64–bit code (see Figure Register section. Bytes 5, 6, and 7 are reserved for inter- 8) stored in ROM. The least significant 8 bits of the ROM nal use by the device and cannot be overwritten. code contain the DS18B20’s 1-Wire family code: 28h. The Byte 8 of the scratchpad is read-only and contains the next 48 bits contain a unique serial number. The most CRC code for bytes 0 through 7 of the scratchpad. significant 8 bits contain a cyclic redundancy check (CRC) The DS18B20 generates this CRC using the method byte that is calculated from the first 56 bits of the ROM described in the CRC Generation section. code. A detailed explanation of the CRC bits is provided Data is written to bytes 2, 3, and 4 of the scratchpad using in the CRC Generation section. The 64-bit ROM code and the Write Scratchpad [4Eh] command; the data must be associated ROM function control logic allow the DS18B20 transmitted to the DS18B20 starting with the least signifi- to operate as a 1-Wire device using the protocol detailed cant bit of byte 2. To verify data integrity, the scratchpad in the 1-Wire Bus System section. can be read (using the Read Scratchpad [BEh] command)
Memory
after the data is written. When reading the scratchpad, data is transferred over the 1-Wire bus starting with the The DS18B20’s memory is organized as shown in Figure least significant bit of byte 0. To transfer the TH, TL and 9. The memory consists of an SRAM scratchpad with configuration data from the scratchpad to EEPROM, the nonvolatile EEPROM storage for the high and low alarm master must issue the Copy Scratchpad [48h] command. trigger registers (TH and TL) and configuration register. Data in the EEPROM registers is retained when the Note that if the DS18B20 alarm function is not used, device is powered down; at power-up the EEPROM data the TH and TL registers can serve as general-purpose is reloaded into the corresponding scratchpad locations. memory. All memory commands are described in detail in Data can also be reloaded from EEPROM to the scratch- the DS18B20 Function Commands section. pad at any time using the Recall E2 [B8h] command. The Byte 0 and byte 1 of the scratchpad contain the LSB and master can issue read time slots following the Recall E2 the MSB of the temperature register, respectively. These command and the DS18B20 will indicate the status of the bytes are read-only. Bytes 2 and 3 provide access to TH recall by transmitting 0 while the recall is in progress and and TL registers. Byte 4 contains the configuration regis- 1 when the recall is done. 8-BIT CRC 48-BIT SERIAL NUMBER 8-BIT FAMILY CODE (28h) MSB LSB MSB LSB MSB LSB Figure 8. 64-Bit Lasered ROM Code
SCRATCHPAD (POWER-UP STATE)
BYTE 0 TEMPERATURE LSB (50h) (85°C) BYTE 1 TEMPERATURE MSB (05h)
EEPROM
BYTE 2 TH REGISTER OR USER BYTE 1* TH REGISTER OR USER BYTE 1* BYTE 3 TL REGISTER OR USER BYTE 2* TL REGISTER OR USER BYTE 2* BYTE 4 CONFIGURATION REGISTER* CONFIGURATION REGISTER* BYTE 5 RESERVED (FFh) BYTE 6 RESERVED BYTE 7 RESERVED (10h) BYTE 8 CRC* *POWER-UP STATE DEPENDS ON VALUE(S) STORED IN EEPROM. Figure 9. DS18B20 Memory Map www.maximintegrated.com Maxim Integrated │
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64-BIT Lasered ROM code
ter data, which is explained in detail in the Configuration Each DS18B20 contains a unique 64–bit code (see Figure Register section. Bytes 5, 6, and 7 are reserved for inter- 8) stored in ROM. The least significant 8 bits of the ROM nal use by the device and cannot be overwritten. code contain the DS18B20’s 1-Wire family code: 28h. The Byte 8 of the scratchpad is read-only and contains the next 48 bits contain a unique serial number. The most CRC code for bytes 0 through 7 of the scratchpad. significant 8 bits contain a cyclic redundancy check (CRC) The DS18B20 generates this CRC using the method byte that is calculated from the first 56 bits of the ROM described in the CRC Generation section. code. A detailed explanation of the CRC bits is provided Data is written to bytes 2, 3, and 4 of the scratchpad using in the CRC Generation section. The 64-bit ROM code and the Write Scratchpad [4Eh] command; the data must be associated ROM function control logic allow the DS18B20 transmitted to the DS18B20 starting with the least signifi- to operate as a 1-Wire device using the protocol detailed cant bit of byte 2. To verify data integrity, the scratchpad in the 1-Wire Bus System section. can be read (using the Read Scratchpad [BEh] command)
Memory
after the data is written. When reading the scratchpad, data is transferred over the 1-Wire bus starting with the The DS18B20’s memory is organized as shown in Figure least significant bit of byte 0. To transfer the TH, TL and 9. The memory consists of an SRAM scratchpad with configuration data from the scratchpad to EEPROM, the nonvolatile EEPROM storage for the high and low alarm master must issue the Copy Scratchpad [48h] command. trigger registers (TH and TL) and configuration register. Data in the EEPROM registers is retained when the Note that if the DS18B20 alarm function is not used, device is powered down; at power-up the EEPROM data the TH and TL registers can serve as general-purpose is reloaded into the corresponding scratchpad locations. memory. All memory commands are described in detail in Data can also be reloaded from EEPROM to the scratch- the DS18B20 Function Commands section. pad at any time using the Recall E2 [B8h] command. The Byte 0 and byte 1 of the scratchpad contain the LSB and master can issue read time slots following the Recall E2 the MSB of the temperature register, respectively. These command and the DS18B20 will indicate the status of the bytes are read-only. Bytes 2 and 3 provide access to TH recall by transmitting 0 while the recall is in progress and and TL registers. Byte 4 contains the configuration regis- 1 when the recall is done. 8-BIT CRC 48-BIT SERIAL NUMBER 8-BIT FAMILY CODE (28h) MSB LSB MSB LSB MSB LSB Figure 8. 64-Bit Lasered ROM Code
SCRATCHPAD (POWER-UP STATE)
BYTE 0 TEMPERATURE LSB (50h) (85°C) BYTE 1 TEMPERATURE MSB (05h)
EEPROM
BYTE 2 TH REGISTER OR USER BYTE 1* TH REGISTER OR USER BYTE 1* BYTE 3 TL REGISTER OR USER BYTE 2* TL REGISTER OR USER BYTE 2* BYTE 4 CONFIGURATION REGISTER* CONFIGURATION REGISTER* BYTE 5 RESERVED (FFh) BYTE 6 RESERVED BYTE 7 RESERVED (10h) BYTE 8 CRC* *POWER-UP STATE DEPENDS ON VALUE(S) STORED IN EEPROM. Figure 9. DS18B20 Memory Map www.maximintegrated.com Maxim Integrated │
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