Datasheet MCP6271, MCP6271R, MCP6272, MCP6273, MCP6274, MCP6275 (Microchip) - 6
| Manufacturer | Microchip |
| Description | Microchip’s MCP62x5 devices are extended industrial-temperature range (-40°C to +125°C), Rail-to-Rail input/output (I/O), single-ended operational amplifiers |
| Pages / Page | 36 / 6 — MCP6271/1R/2/3/4/5. 2.0. TYPICAL PERFORMANCE CURVES. Note:. 18%. 14%. 832 … |
| File Format / Size | PDF / 668 Kb |
| Document Language | English |
MCP6271/1R/2/3/4/5. 2.0. TYPICAL PERFORMANCE CURVES. Note:. 18%. 14%. 832 Samples. 16%. ces 12%. CM = VSS. VCM = VSS. rren
Model Line for this Datasheet
Text Version of Document
MCP6271/1R/2/3/4/5 2.0 TYPICAL PERFORMANCE CURVES Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note:
Unless otherwise indicated, T ≈ A = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS is tied low.
18% 14% s 832 Samples 832 Samples 16% ce V ces 12% CM = VSS VCM = VSS 14% en rren TA = -40°C to +125°C u rr 10% 12% 10% ccu Occ 8% 8% f O of e o 6% g 6% e g ta 4% ta 4% en rcen 2% 2% Pe 0% Perc 0 4 8 2 6 0 6 2 8 4 0 0% 0 -3. -2. -1. -1. -0. 0. 0. 1. 1. 2. 3. -8 -6 -4 -2 0 2 4 6 8 -1 10 Input Offset Voltage (mV) Input Offset Voltage Drift (µV/°C) FIGURE 2-1:
Input Offset Voltage.
FIGURE 2-4:
Input Offset Voltage Drift.
32% 22% 422 Samples 20% 422 Samples 28% ces TA = 85°C es 18% TA = +125°C c en 24% n 16% rr u 20% 14% curre 12% Occ 16% 10% of e 12% of Oc 8% g e ta g 6% 8% ta 4% n cen 4% 2% Per 0% 0% Perce 6 8 0 2 4 6 8 0 2 4 6 8 0 0 10 20 30 40 50 60 70 80 90 100 0. 0. 1. 1. 1. 1. 1. 2. 2. 2. 2. 2. 3. Input Bias Current (pA) Input Bias Current (nA) FIGURE 2-2:
Input Bias Current at
FIGURE 2-5:
Input Bias Current at TA = +85°C. TA = +125°C.
300 300 ) VDD = 2.0V VDD = 5.5V V 250 250 V) µ 200 e (µ 200 e ( ag 150 lt 150 ltag T o o A = +125°C 100 t V V 100 T et 50 A = +125°C fse 50 TA = +85°C ffs TA = +85°C 0 t Of T t O 0 T u A = +25°C A = +25°C p -50 T pu T In A = -40°C -50 A = -40°C In -100 -100 4 2 0 2 4 6 8 0 2 4 6 8 0 2 4 .5 0 5 0 5 0 5 0 5 0 5 0 5 0 -0. -0. 0. 0. 0. 0. 0. 1. 1. 1. 1. 1. 2. 2. 2. -0 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. Common Mode Input Voltage (V) Common Mode Input Voltage (V) FIGURE 2-3:
Input Offset Voltage vs.
FIGURE 2-6:
Input Offset Voltage vs. Common Mode Input Voltage, with VDD = 2.0V. Common Mode Input Voltage, with VDD = 5.5V. DS21810F-page 6 © 2008 Microchip Technology Inc. Document Outline 1.0 Electrical Characteristics FIGURE 1-1: Timing Diagram for the Chip Select (CS) pin on the MCP6273 and MCP6275. 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Bias Current at TA = +85˚C. FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage, with VDD = 2.0V. FIGURE 2-4: Input Offset Voltage Drift. FIGURE 2-5: Input Bias Current at TA = +125˚C. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage, with VDD = 5.5V. FIGURE 2-7: Common Mode Input Voltage Range Lower Limit vs. Temperature. FIGURE 2-8: Input Offset Voltage vs. Output Voltage. FIGURE 2-9: CMRR, PSRR vs. Frequency. FIGURE 2-10: Common Mode Input Voltage Range Upper Limit vs. Temperature. FIGURE 2-11: Input Bias, Input Offset Currents vs. Temperature. FIGURE 2-12: CMRR, PSRR vs. Temperature. FIGURE 2-13: Input Bias, Offset Currents vs. Common Mode Input Voltage, with TA = +85˚C. FIGURE 2-14: Quiescent Current vs. Supply Voltage. FIGURE 2-15: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-16: Input Bias, Offset Currents vs. Common Mode Input Voltage, with TA = +125˚C. FIGURE 2-17: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-18: Gain Bandwidth Product, Phase Margin vs. Temperature. FIGURE 2-19: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-20: Input Noise Voltage Density vs. Frequency. FIGURE 2-21: Output Short Circuit Current vs. Supply Voltage. FIGURE 2-22: Slew Rate vs. Temperature. FIGURE 2-23: Input Noise Voltage Density vs. Common Mode Input Voltage, with f = 1 kHz. FIGURE 2-24: Channel-to-Channel Separation vs. Frequency (MCP6272 and MCP6274). FIGURE 2-25: Quiescent Current vs. Chip Select (CS) Voltage, with VDD = 2.0V (MCP6273 and MCP6275 only). FIGURE 2-26: Large Signal Non-inverting Pulse Response. FIGURE 2-27: Small Signal Non-inverting Pulse Response. FIGURE 2-28: Quiescent Current vs. Chip Select (CS) Voltage, with VDD = 5.5V (MCP6273 and MCP6275 only). FIGURE 2-29: Large Signal Inverting Pulse Response. FIGURE 2-30: Small Signal Inverting Pulse Response. FIGURE 2-31: Chip Select (CS) to Amplifier Output Response Time, with VDD = 2.0V (MCP6273 and MCP6275 only). FIGURE 2-32: Input Current vs. Input Voltage. FIGURE 2-33: Chip Select (CS) to Amplifier Output Response Time, with VDD = 5,5V (MCP6273 and MCP6275 only). FIGURE 2-34: The MCP6271/1R/2/3/4/5 Show no Phase Reversal. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table for Single Op Amps TABLE 3-2: Pin Function Table for Dual and Quad Op Amps 3.1 Analog Outputs 3.2 Analog Inputs 3.3 MCP6275’s VOUTA/VINB+ Pin 3.4 Chip Select Digital Input 3.5 Power Supply Pins 4.0 Application Information 4.1 Rail-to-Rail Inputs FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-3: Output Resistor, RISO stabilizes large capacitive loads. FIGURE 4-4: Recommended RISO Values for Capacitive Loads. 4.4 MCP6273/5 Chip Select 4.5 Cascaded Dual Op Amps (MCP6275) FIGURE 4-5: Cascaded Gain Amplifier. 4.6 Unused Amplifiers FIGURE 4-6: Unused Op Amps. 4.7 Supply Bypass 4.8 PCB Surface Leakage FIGURE 4-7: Example Guard Ring Layout for Inverting Gain. 4.9 Application Circuits FIGURE 4-8: Active Full-wave Rectifier. FIGURE 4-9: Non-Inverting Integrator. FIGURE 4-10: Isolating the Load with a Buffer. FIGURE 4-11: Cascaded Gain Circuit Configuration. FIGURE 4-12: Difference Amplifier Circuit. FIGURE 4-13: Integrator Circuit with Active Compensation. FIGURE 4-14: Second Order Multiple Feedback Low-Pass Filter with an Extra Pole- Zero Pair. FIGURE 4-15: Second Order Sallen-Key Low-Pass Filter with an Extra Pole-Zero Pair and Chip Select. FIGURE 4-16: Capacitorless Second Order Low-Pass Filter with Chip Select. 5.0 Design Tools 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Circuit Designer & Simulator 5.4 MAPS (Microchip Advanced Part Selector) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note:
Unless otherwise indicated, T ≈ A = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS is tied low.
18% 14% s 832 Samples 832 Samples 16% ce V ces 12% CM = VSS VCM = VSS 14% en rren TA = -40°C to +125°C u rr 10% 12% 10% ccu Occ 8% 8% f O of e o 6% g 6% e g ta 4% ta 4% en rcen 2% 2% Pe 0% Perc 0 4 8 2 6 0 6 2 8 4 0 0% 0 -3. -2. -1. -1. -0. 0. 0. 1. 1. 2. 3. -8 -6 -4 -2 0 2 4 6 8 -1 10 Input Offset Voltage (mV) Input Offset Voltage Drift (µV/°C) FIGURE 2-1:
Input Offset Voltage.
FIGURE 2-4:
Input Offset Voltage Drift.
32% 22% 422 Samples 20% 422 Samples 28% ces TA = 85°C es 18% TA = +125°C c en 24% n 16% rr u 20% 14% curre 12% Occ 16% 10% of e 12% of Oc 8% g e ta g 6% 8% ta 4% n cen 4% 2% Per 0% 0% Perce 6 8 0 2 4 6 8 0 2 4 6 8 0 0 10 20 30 40 50 60 70 80 90 100 0. 0. 1. 1. 1. 1. 1. 2. 2. 2. 2. 2. 3. Input Bias Current (pA) Input Bias Current (nA) FIGURE 2-2:
Input Bias Current at
FIGURE 2-5:
Input Bias Current at TA = +85°C. TA = +125°C.
300 300 ) VDD = 2.0V VDD = 5.5V V 250 250 V) µ 200 e (µ 200 e ( ag 150 lt 150 ltag T o o A = +125°C 100 t V V 100 T et 50 A = +125°C fse 50 TA = +85°C ffs TA = +85°C 0 t Of T t O 0 T u A = +25°C A = +25°C p -50 T pu T In A = -40°C -50 A = -40°C In -100 -100 4 2 0 2 4 6 8 0 2 4 6 8 0 2 4 .5 0 5 0 5 0 5 0 5 0 5 0 5 0 -0. -0. 0. 0. 0. 0. 0. 1. 1. 1. 1. 1. 2. 2. 2. -0 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. Common Mode Input Voltage (V) Common Mode Input Voltage (V) FIGURE 2-3:
Input Offset Voltage vs.
FIGURE 2-6:
Input Offset Voltage vs. Common Mode Input Voltage, with VDD = 2.0V. Common Mode Input Voltage, with VDD = 5.5V. DS21810F-page 6 © 2008 Microchip Technology Inc. Document Outline 1.0 Electrical Characteristics FIGURE 1-1: Timing Diagram for the Chip Select (CS) pin on the MCP6273 and MCP6275. 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Bias Current at TA = +85˚C. FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage, with VDD = 2.0V. FIGURE 2-4: Input Offset Voltage Drift. FIGURE 2-5: Input Bias Current at TA = +125˚C. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage, with VDD = 5.5V. FIGURE 2-7: Common Mode Input Voltage Range Lower Limit vs. Temperature. FIGURE 2-8: Input Offset Voltage vs. Output Voltage. FIGURE 2-9: CMRR, PSRR vs. Frequency. FIGURE 2-10: Common Mode Input Voltage Range Upper Limit vs. Temperature. FIGURE 2-11: Input Bias, Input Offset Currents vs. Temperature. FIGURE 2-12: CMRR, PSRR vs. Temperature. FIGURE 2-13: Input Bias, Offset Currents vs. Common Mode Input Voltage, with TA = +85˚C. FIGURE 2-14: Quiescent Current vs. Supply Voltage. FIGURE 2-15: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-16: Input Bias, Offset Currents vs. Common Mode Input Voltage, with TA = +125˚C. FIGURE 2-17: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-18: Gain Bandwidth Product, Phase Margin vs. Temperature. FIGURE 2-19: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-20: Input Noise Voltage Density vs. Frequency. FIGURE 2-21: Output Short Circuit Current vs. Supply Voltage. FIGURE 2-22: Slew Rate vs. Temperature. FIGURE 2-23: Input Noise Voltage Density vs. Common Mode Input Voltage, with f = 1 kHz. FIGURE 2-24: Channel-to-Channel Separation vs. Frequency (MCP6272 and MCP6274). FIGURE 2-25: Quiescent Current vs. Chip Select (CS) Voltage, with VDD = 2.0V (MCP6273 and MCP6275 only). FIGURE 2-26: Large Signal Non-inverting Pulse Response. FIGURE 2-27: Small Signal Non-inverting Pulse Response. FIGURE 2-28: Quiescent Current vs. Chip Select (CS) Voltage, with VDD = 5.5V (MCP6273 and MCP6275 only). FIGURE 2-29: Large Signal Inverting Pulse Response. FIGURE 2-30: Small Signal Inverting Pulse Response. FIGURE 2-31: Chip Select (CS) to Amplifier Output Response Time, with VDD = 2.0V (MCP6273 and MCP6275 only). FIGURE 2-32: Input Current vs. Input Voltage. FIGURE 2-33: Chip Select (CS) to Amplifier Output Response Time, with VDD = 5,5V (MCP6273 and MCP6275 only). FIGURE 2-34: The MCP6271/1R/2/3/4/5 Show no Phase Reversal. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table for Single Op Amps TABLE 3-2: Pin Function Table for Dual and Quad Op Amps 3.1 Analog Outputs 3.2 Analog Inputs 3.3 MCP6275’s VOUTA/VINB+ Pin 3.4 Chip Select Digital Input 3.5 Power Supply Pins 4.0 Application Information 4.1 Rail-to-Rail Inputs FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-3: Output Resistor, RISO stabilizes large capacitive loads. FIGURE 4-4: Recommended RISO Values for Capacitive Loads. 4.4 MCP6273/5 Chip Select 4.5 Cascaded Dual Op Amps (MCP6275) FIGURE 4-5: Cascaded Gain Amplifier. 4.6 Unused Amplifiers FIGURE 4-6: Unused Op Amps. 4.7 Supply Bypass 4.8 PCB Surface Leakage FIGURE 4-7: Example Guard Ring Layout for Inverting Gain. 4.9 Application Circuits FIGURE 4-8: Active Full-wave Rectifier. FIGURE 4-9: Non-Inverting Integrator. FIGURE 4-10: Isolating the Load with a Buffer. FIGURE 4-11: Cascaded Gain Circuit Configuration. FIGURE 4-12: Difference Amplifier Circuit. FIGURE 4-13: Integrator Circuit with Active Compensation. FIGURE 4-14: Second Order Multiple Feedback Low-Pass Filter with an Extra Pole- Zero Pair. FIGURE 4-15: Second Order Sallen-Key Low-Pass Filter with an Extra Pole-Zero Pair and Chip Select. FIGURE 4-16: Capacitorless Second Order Low-Pass Filter with Chip Select. 5.0 Design Tools 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Circuit Designer & Simulator 5.4 MAPS (Microchip Advanced Part Selector) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information
