Datasheet ADA4627-1, ADA4637-1 (Analog Devices) - 17
| Manufacturer | Analog Devices |
| Description | 30 V, 80 MHz, Low Noise, Low Bias Current, JFET Op Amp |
| Pages / Page | 20 / 17 — Data Sheet. ADA4627-1/ADA4637-1. OUTLINE DIMENSIONS. 1.84. 3.10. 1.74. … |
| Revision | F |
| File Format / Size | PDF / 793 Kb |
| Document Language | English |
Data Sheet. ADA4627-1/ADA4637-1. OUTLINE DIMENSIONS. 1.84. 3.10. 1.74. 3.00 SQ. 1.64. 2.90. 0.50 BSC. PIN 1 INDEX. EXPOSED. 1.55. AREA. PAD
Model Line for this Datasheet
Text Version of Document
Data Sheet ADA4627-1/ADA4637-1 OUTLINE DIMENSIONS 1.84 3.10 1.74 3.00 SQ 1.64 2.90 0.50 BSC 5 8 PIN 1 INDEX EXPOSED 1.55 AREA PAD 1.45 1.35 0.50 0.40 0.30 4 1 PIN 1 TOP VIEW BOTTOM VIEW INDICATOR (R 0.15) 0.80 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO 0.75 0.05 MAX THE PIN CONFIGURATION AND 0.70 0.02 NOM FUNCTION DESCRIPTIONS COPLANARITY SECTION OF THIS DATA SHEET. SEATING 0.30 0.08 PLANE 0.25 0.203 REF -A 0.20 0 1 0 -2 7 -0 COMPLIANT TO JEDEC STANDARDS MO-229-WEED 2 1
Figure 52. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-8-13) Dimensions shown in millimeters
5.00 (0.1968) 4.80 (0.1890) 8 5 4.00 (0.1574) 6.20 (0.2441) 1 3.80 (0.1497) 5.80 (0.2284) 4 1.27 (0.0500) 0.50 (0.0196) 45° BSC 1.75 (0.0688) 0.25 (0.0099) 1.35 (0.0532) 0.25 (0.0098) 8° 0.10 (0.0040) 0° COPLANARITY 0.51 (0.0201) 1.27 (0.0500) 0.10 0.31 (0.0122) 0.25 (0.0098) SEATING 0.40 (0.0157) PLANE 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS A-7 (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR 0 4 2 REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 1 0
Figure 53. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) Rev. F | Page 17 of 20 Document Outline FEATURES APPLICATIONS PIN CONFIGURATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS—30 V OPERATION ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION INPUT VOLTAGE RANGE INPUT OFFSET VOLTAGE ADJUST RANGE INPUT BIAS CURRENT NOISE CONSIDERATIONS THD + N MEASUREMENTS PRINTED CIRCUIT BOARD LAYOUT, BIAS CURRENT, AND BYPASSING OUTPUT PHASE REVERSAL DECOMPENSATED OP AMPS DRIVING CAPACITIVE LOADS OUTLINE DIMENSIONS ORDERING GUIDE
Figure 52. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-8-13) Dimensions shown in millimeters
5.00 (0.1968) 4.80 (0.1890) 8 5 4.00 (0.1574) 6.20 (0.2441) 1 3.80 (0.1497) 5.80 (0.2284) 4 1.27 (0.0500) 0.50 (0.0196) 45° BSC 1.75 (0.0688) 0.25 (0.0099) 1.35 (0.0532) 0.25 (0.0098) 8° 0.10 (0.0040) 0° COPLANARITY 0.51 (0.0201) 1.27 (0.0500) 0.10 0.31 (0.0122) 0.25 (0.0098) SEATING 0.40 (0.0157) PLANE 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS A-7 (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR 0 4 2 REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 1 0
Figure 53. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) Rev. F | Page 17 of 20 Document Outline FEATURES APPLICATIONS PIN CONFIGURATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS—30 V OPERATION ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION INPUT VOLTAGE RANGE INPUT OFFSET VOLTAGE ADJUST RANGE INPUT BIAS CURRENT NOISE CONSIDERATIONS THD + N MEASUREMENTS PRINTED CIRCUIT BOARD LAYOUT, BIAS CURRENT, AND BYPASSING OUTPUT PHASE REVERSAL DECOMPENSATED OP AMPS DRIVING CAPACITIVE LOADS OUTLINE DIMENSIONS ORDERING GUIDE
