Datasheet AD8007, AD8008 (Analog Devices) - 16
| Manufacturer | Analog Devices |
| Description | Ultralow Distortion, High Speed Amplifiers |
| Pages / Page | 20 / 16 — AD8007/AD8008. LAYOUT CONSIDERATIONS. 499Ω. 10µF. +VS. 0.1µF. AD8007. … |
| Revision | E |
| File Format / Size | PDF / 374 Kb |
| Document Language | English |
AD8007/AD8008. LAYOUT CONSIDERATIONS. 499Ω. 10µF. +VS. 0.1µF. AD8007. OUT. 200Ω. –VS
Model Line for this Datasheet
Text Version of Document
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AD8007/AD8008
Whenever physical layout considerations prevent the decoupling
LAYOUT CONSIDERATIONS
scheme shown in Figure 53, the user can connect one of the The standard noninverting configuration with recommended high frequency decoupling capacitors directly across the supplies power supply bypassing is shown in Figure 54. The 0.1 μF high and connect the other high frequency decoupling capacitor to frequency decoupling capacitors should be X7R or NPO chip ground (see Figure 54). components. Connect C2 from the +VS pin to the −VS pin.
RF
Connect C1 from the +V
499Ω
S pin to signal ground. The length of the high frequency bypass capacitor leads is critical.
10µF +
Parasitic inductance due to long leads works against the low
+VS
impedance created by the bypass capacitor. The ground for the
C1 0.1µF
load impedance should be at the same physical location as the
RG
bypass capacitor grounds. For larger value capacitors, which are
499Ω
intended to be effective at lower frequencies, the current return
RS AD8007 OUT
path distance is less critical.
200Ω IN C2 0.1µF –VS 10µF
54
+
0 6- 86 02 Figure 54. High Frequency Capacitors Connected Across the Supplies (Recommended) Rev. E | Page 16 of 20 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION CONNECTION DIAGRAMS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS VS = ±5 V VS = 5 V ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION OUTPUT SHORT CIRCUIT ESD CAUTION TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION USING THE AD8007/AD8008 Supply Decoupling for Low Distortion LAYOUT CONSIDERATIONS LAYOUT AND GROUNDING CONSIDERATIONS GROUNDING INPUT CAPACITANCE OUTPUT CAPACITANCE INPUT-TO-OUTPUT COUPLING EXTERNAL COMPONENTS AND STABILITY OUTLINE DIMENSIONS ORDERING GUIDE
AD8007/AD8008
Whenever physical layout considerations prevent the decoupling
LAYOUT CONSIDERATIONS
scheme shown in Figure 53, the user can connect one of the The standard noninverting configuration with recommended high frequency decoupling capacitors directly across the supplies power supply bypassing is shown in Figure 54. The 0.1 μF high and connect the other high frequency decoupling capacitor to frequency decoupling capacitors should be X7R or NPO chip ground (see Figure 54). components. Connect C2 from the +VS pin to the −VS pin.
RF
Connect C1 from the +V
499Ω
S pin to signal ground. The length of the high frequency bypass capacitor leads is critical.
10µF +
Parasitic inductance due to long leads works against the low
+VS
impedance created by the bypass capacitor. The ground for the
C1 0.1µF
load impedance should be at the same physical location as the
RG
bypass capacitor grounds. For larger value capacitors, which are
499Ω
intended to be effective at lower frequencies, the current return
RS AD8007 OUT
path distance is less critical.
200Ω IN C2 0.1µF –VS 10µF
54
+
0 6- 86 02 Figure 54. High Frequency Capacitors Connected Across the Supplies (Recommended) Rev. E | Page 16 of 20 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION CONNECTION DIAGRAMS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS VS = ±5 V VS = 5 V ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION OUTPUT SHORT CIRCUIT ESD CAUTION TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION USING THE AD8007/AD8008 Supply Decoupling for Low Distortion LAYOUT CONSIDERATIONS LAYOUT AND GROUNDING CONSIDERATIONS GROUNDING INPUT CAPACITANCE OUTPUT CAPACITANCE INPUT-TO-OUTPUT COUPLING EXTERNAL COMPONENTS AND STABILITY OUTLINE DIMENSIONS ORDERING GUIDE