Datasheet LTC1290 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Single Chip 12-Bit Data Acquisition System |
| Pages / Page | 32 / 10 — APPLICATI. S I FOR ATIO. DIGITAL CONSIDERATIONS. Serial Interface. Input … |
| File Format / Size | PDF / 633 Kb |
| Document Language | English |
APPLICATI. S I FOR ATIO. DIGITAL CONSIDERATIONS. Serial Interface. Input Data Word. Operating Sequence
Model Line for this Datasheet
- LTC1290BCN#PBF LTC1290BCN#PBF LTC1290BCSW#PBF LTC1290BCSW#PBF LTC1290BCSW#TRPBF LTC1290BCSW#TRPBF LTC1290BIN#PBF LTC1290BIN#PBF LTC1290BISW#PBF LTC1290BISW#PBF LTC1290BISW#TRPBF LTC1290BISW#TRPBF LTC1290CCN#PBF LTC1290CCN#PBF LTC1290CCSW#PBF LTC1290CCSW#PBF LTC1290CCSW#TRPBF LTC1290CCSW#TRPBF LTC1290CIN#PBF LTC1290CIN#PBF LTC1290CISW#PBF LTC1290CISW#PBF LTC1290CISW#TRPBF LTC1290CISW#TRPBF LTC1290DCN#PBF LTC1290DCN#PBF LTC1290DCSW#PBF LTC1290DCSW#PBF LTC1290DCSW#TRPBF LTC1290DCSW#TRPBF LTC1290DIN#PBF LTC1290DIN#PBF LTC1290DISW#PBF LTC1290DISW#PBF LTC1290DISW#TRPBF LTC1290DISW#TRPBF
Text Version of Document
LTC1290
O U U W U APPLICATI S I FOR ATIO
The LTC1290 is a data acquisition component which previous conversion is output on the DOUT line. At the end contains the following functional blocks: of the data exchange the requested conversion begins and CS should be brought high. After tCONV, the conversion is 1. 12-bit successive approximation capacitive A/D complete and the results will be available on the next data converter transfer cycle. As shown below, the result of a conversion 2. Analog multiplexer (MUX) is delayed by one CS cycle from the input word requesting it. 3. Sample-and-hold (S/H) 4. Synchronous, full duplex serial interface D D D D 5. Control and timing logic IN IN WORD 1 IN WORD 2 IN WORD 3 DOUT DOUT WORD 0 D D OUT WORD 1 OUT WORD 2
DIGITAL CONSIDERATIONS
t t DATA CONV DATA CONV A/D A/D TRANSFER TRANSFER
Serial Interface
CONVERSION CONVERSION LTC1290 • AI01 The LTC1290 communicates with microprocessors and
Input Data Word
other external circuitry via a synchronous, full duplex, four-wire serial interface (see Operating Sequence). The The LTC1290 8-bit data word is clocked into the DIN input shift clock (SCLK) synchronizes the data transfer with on the first eight rising SCLK edges after chip select is each bit being transmitted on the falling SCLK edge and recognized. Further inputs on the DIN pin are then ignored captured on the rising SCLK edge in both transmitting and until the next CS cycle. The eight bits of the input word are receiving systems. The data is transmitted and received defined as follows: simultaneously (full duplex). UNIPOLAR/ WORD BIPOLAR LENGTH Data transfer is initiated by a falling chip select (CS) signal. SGL/ ODD/ SELECT SELECT After the falling CS is recognized, an 8-bit input word is UNI MSBF WL1 WL0 DIFF SIGN 1 0 shifted into the DIN input which configures the LTC1290 for the next conversion. Simultaneously, the result of the MUX ADDRESS MSB-FIRST/ LSB-FIRST LTC1290 • AI02
Operating Sequence (Example: Differential Inputs (CH3-CH2), Bipolar, MSB-First and 12-Bit Word Length)
tCYC 1 2 3 4 5 6 7 8 9 10 11 12 SCLK DON’T CARE t t SMPL CONV CS DIN DON’T CARE D B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 OUT SHIFT CONFIGURATION (SB) SHIFT A/D RESULT OUT AND WORD IN NEW CONFIGURATION WORD IN LTC1290 • AI03 1290fe 10
O U U W U APPLICATI S I FOR ATIO
The LTC1290 is a data acquisition component which previous conversion is output on the DOUT line. At the end contains the following functional blocks: of the data exchange the requested conversion begins and CS should be brought high. After tCONV, the conversion is 1. 12-bit successive approximation capacitive A/D complete and the results will be available on the next data converter transfer cycle. As shown below, the result of a conversion 2. Analog multiplexer (MUX) is delayed by one CS cycle from the input word requesting it. 3. Sample-and-hold (S/H) 4. Synchronous, full duplex serial interface D D D D 5. Control and timing logic IN IN WORD 1 IN WORD 2 IN WORD 3 DOUT DOUT WORD 0 D D OUT WORD 1 OUT WORD 2
DIGITAL CONSIDERATIONS
t t DATA CONV DATA CONV A/D A/D TRANSFER TRANSFER
Serial Interface
CONVERSION CONVERSION LTC1290 • AI01 The LTC1290 communicates with microprocessors and
Input Data Word
other external circuitry via a synchronous, full duplex, four-wire serial interface (see Operating Sequence). The The LTC1290 8-bit data word is clocked into the DIN input shift clock (SCLK) synchronizes the data transfer with on the first eight rising SCLK edges after chip select is each bit being transmitted on the falling SCLK edge and recognized. Further inputs on the DIN pin are then ignored captured on the rising SCLK edge in both transmitting and until the next CS cycle. The eight bits of the input word are receiving systems. The data is transmitted and received defined as follows: simultaneously (full duplex). UNIPOLAR/ WORD BIPOLAR LENGTH Data transfer is initiated by a falling chip select (CS) signal. SGL/ ODD/ SELECT SELECT After the falling CS is recognized, an 8-bit input word is UNI MSBF WL1 WL0 DIFF SIGN 1 0 shifted into the DIN input which configures the LTC1290 for the next conversion. Simultaneously, the result of the MUX ADDRESS MSB-FIRST/ LSB-FIRST LTC1290 • AI02
Operating Sequence (Example: Differential Inputs (CH3-CH2), Bipolar, MSB-First and 12-Bit Word Length)
tCYC 1 2 3 4 5 6 7 8 9 10 11 12 SCLK DON’T CARE t t SMPL CONV CS DIN DON’T CARE D B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 OUT SHIFT CONFIGURATION (SB) SHIFT A/D RESULT OUT AND WORD IN NEW CONFIGURATION WORD IN LTC1290 • AI03 1290fe 10
