Datasheet LTC2208-14 (Analog Devices)
| Manufacturer | Analog Devices |
| Description | 14-Bit, 130Msps ADC |
| Pages / Page | 28 / 1 — FEATURES. DESCRIPTION. Sample Rate: 130Msps. 77.1dBFS Noise Floor. 98dB … |
| File Format / Size | PDF / 730 Kb |
| Document Language | English |
FEATURES. DESCRIPTION. Sample Rate: 130Msps. 77.1dBFS Noise Floor. 98dB SFDR. SFDR >81dB at 250MHz (1.5VP-P Input Range)
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LTC2208-14 14-Bit, 130Msps ADC
FEATURES DESCRIPTION
n
Sample Rate: 130Msps
The LTC®2208-14 is a 130Msps, sampling 14-bit A/D n
77.1dBFS Noise Floor
converter designed for digitizing high frequency, wide n
98dB SFDR
dynamic range signals with input frequencies up to n
SFDR >81dB at 250MHz (1.5VP-P Input Range)
700MHz. The input range of the ADC can be optimized n
PGA Front End (2.25VP-P or 1.5VP-P Input Range)
with the PGA front end. n
700MHz Full Power Bandwidth S/H
The LTC2208-14 is perfect for demanding communications n
Optional Internal Dither
applications, with AC performance that includes 77.1dBFS n
Optional Data Output Randomizer
Noise Floor and 98dB spurious free dynamic range (SFDR). n LVDS or CMOS Outputs Ultralow jitter of 70fsRMS allows undersampling of high n Single 3.3V Supply input frequencies with excellent noise performance. n Power Dissipation: 1.32W Maximum DC specs include ±1.5LSB INL, ±0.5LSB DNL n Clock Duty Cycle Stabilizer (no missing codes). n Pin Compatible 16-Bit Version 130Msps: LTC2208 (16-Bit) The digital output can be either differential LVDS or n 64-Pin (9mm single-ended CMOS. There are two format options for the × 9mm) QFN Package CMOS outputs: a single bus running at the full data rate or
APPLICATIONS
demultiplexed buses running at half data rate. A separate output power supply allows the CMOS output swing to n Telecommunications range from 0.5V to 3.6V. n Receivers n Cellular Base Stations The ENC+ and ENC– inputs may be driven differentially n Spectrum Analysis or single-ended with a sine wave, PECL, LVDS, TTL or n Imaging Systems CMOS inputs. An optional clock duty cycle stabilizer al- n ATE lows high performance at full speed with a wide range of L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear clock duty cycles. Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
3.3V
32k Point FFT, fIN = 15.11MHz,
SENSE
–1dB, PGA = 0, RAND “On”,
OVDD
Dither “OFF”
1.25V INTERNAL ADC VCM 0.5V TO 3.6V COMMON MODE REFERENCE 0 2.2μF BIAS VOLTAGE GENERATOR 0.1μF –10 –20 OF AIN+ –30 + CLKOUT 14-BIT CORRECTION OUTPUT D13 CMOS –40 ANALOG S/H PIPELINED LOGIC AND DRIVERS • OR INPUT AMP –50 ADC CORE SHIFT REGISTER LVDS – • –60 AIN– • D0 –70 –80 OGND AMPLITUDE (dBFS) –90 CLOCK/DUTY –100 CYCLE V 3.3V DD CONTROL –110 0.1μF 0.1μF GND –120 0.1μF 0 10 20 30 40 50 60 220814 TA01 FREQUENCY (MHz) ENC + ENC – PGA SHDN DITH MODE LVDS RAND 220814 G05 ADC CONTROL INPUTS 220814fb 1
FEATURES DESCRIPTION
n
Sample Rate: 130Msps
The LTC®2208-14 is a 130Msps, sampling 14-bit A/D n
77.1dBFS Noise Floor
converter designed for digitizing high frequency, wide n
98dB SFDR
dynamic range signals with input frequencies up to n
SFDR >81dB at 250MHz (1.5VP-P Input Range)
700MHz. The input range of the ADC can be optimized n
PGA Front End (2.25VP-P or 1.5VP-P Input Range)
with the PGA front end. n
700MHz Full Power Bandwidth S/H
The LTC2208-14 is perfect for demanding communications n
Optional Internal Dither
applications, with AC performance that includes 77.1dBFS n
Optional Data Output Randomizer
Noise Floor and 98dB spurious free dynamic range (SFDR). n LVDS or CMOS Outputs Ultralow jitter of 70fsRMS allows undersampling of high n Single 3.3V Supply input frequencies with excellent noise performance. n Power Dissipation: 1.32W Maximum DC specs include ±1.5LSB INL, ±0.5LSB DNL n Clock Duty Cycle Stabilizer (no missing codes). n Pin Compatible 16-Bit Version 130Msps: LTC2208 (16-Bit) The digital output can be either differential LVDS or n 64-Pin (9mm single-ended CMOS. There are two format options for the × 9mm) QFN Package CMOS outputs: a single bus running at the full data rate or
APPLICATIONS
demultiplexed buses running at half data rate. A separate output power supply allows the CMOS output swing to n Telecommunications range from 0.5V to 3.6V. n Receivers n Cellular Base Stations The ENC+ and ENC– inputs may be driven differentially n Spectrum Analysis or single-ended with a sine wave, PECL, LVDS, TTL or n Imaging Systems CMOS inputs. An optional clock duty cycle stabilizer al- n ATE lows high performance at full speed with a wide range of L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear clock duty cycles. Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
3.3V
32k Point FFT, fIN = 15.11MHz,
SENSE
–1dB, PGA = 0, RAND “On”,
OVDD
Dither “OFF”
1.25V INTERNAL ADC VCM 0.5V TO 3.6V COMMON MODE REFERENCE 0 2.2μF BIAS VOLTAGE GENERATOR 0.1μF –10 –20 OF AIN+ –30 + CLKOUT 14-BIT CORRECTION OUTPUT D13 CMOS –40 ANALOG S/H PIPELINED LOGIC AND DRIVERS • OR INPUT AMP –50 ADC CORE SHIFT REGISTER LVDS – • –60 AIN– • D0 –70 –80 OGND AMPLITUDE (dBFS) –90 CLOCK/DUTY –100 CYCLE V 3.3V DD CONTROL –110 0.1μF 0.1μF GND –120 0.1μF 0 10 20 30 40 50 60 220814 TA01 FREQUENCY (MHz) ENC + ENC – PGA SHDN DITH MODE LVDS RAND 220814 G05 ADC CONTROL INPUTS 220814fb 1
