Datasheet LTC2242-10 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 10-Bit, 250Msps ADC |
| Pages / Page | 30 / 10 — pin FuncTions (LVDS Mode) AIN+ (Pins 1, 2):. OGND (Pins 25, 33, 41, 50):. … |
| File Format / Size | PDF / 602 Kb |
| Document Language | English |
pin FuncTions (LVDS Mode) AIN+ (Pins 1, 2):. OGND (Pins 25, 33, 41, 50):. AIN– (Pins 3, 4):. OVDD (Pins 26, 34, 42, 49):
Model Line for this Datasheet
Text Version of Document
LTC2242-10
pin FuncTions (LVDS Mode) AIN+ (Pins 1, 2):
Positive Differential Analog Input.
OGND (Pins 25, 33, 41, 50):
Output Driver Ground.
AIN– (Pins 3, 4):
Negative Differential Analog Input.
OVDD (Pins 26, 34, 42, 49):
Positive Supply for the Out-
REFHA (Pins 5, 6):
ADC High Reference. Bypass to put Drivers. Bypass to ground with 0.1µF ceramic chip Pins 7, 8 with 0.1µF ceramic chip capacitor, to Pins 11, capacitor. 12 with a 2.2µF ceramic capacitor and to ground with 1µF
CLKOUT–/CLKOUT+ (Pins 35 to 36):
LVDS Data Valid ceramic capacitor. Output. Latch data on rising edge of CLKOUT–, falling
REFLB (Pins 7, 8):
ADC Low Reference. Bypass to Pins edge of CLKOUT+. 5, 6 with 0.1µF ceramic chip capacitor. Do not connect to
OF–/OF+ (Pins 55 to 56):
LVDS Over/Under Flow Output. Pins 11, 12. High when an over or under flow has occurred.
REFHB (Pins 9, 10):
ADC High Reference. Bypass to
LVDS (Pin 57):
Output Mode Selection Pin. Connecting Pins 11, 12 with 0.1µF ceramic chip capacitor. Do not LVDS to 0V selects full rate CMOS mode. Connecting LVDS connect to Pins 5, 6. to 1/3VDD selects demux CMOS mode with simultaneous
REFLA (Pins 11, 12):
ADC Low Reference. Bypass to update. Connecting LVDS to 2/3VDD selects demux CMOS Pins 9, 10 with 0.1µF ceramic chip capacitor, to Pins 5, mode with interleaved update. Connecting LVDS to VDD 6 with a 2.2µF ceramic capacitor and to ground with 1µF selects LVDS mode. ceramic capacitor.
MODE (Pin 58):
Output Format and Clock Duty Cycle
V
Stabilizer Selection Pin. Connecting MODE to 0V selects
DD (Pins 13, 14, 15, 62, 63):
2.5V Supply. Bypass to GND with 0.1µF ceramic chip capacitors. offset binary output format and turns the clock duty cycle stabilizer off. Connecting MODE to 1/3V
GND (Pins 16, 61, 64):
ADC Power Ground. DD selects offset binary output format and turns the clock duty cycle stabilizer
ENC+ (Pin 17):
Encode Input. Conversion starts on the on. Connecting MODE to 2/3VDD selects 2’s complement positive edge. output format and turns the clock duty cycle stabilizer on.
ENC– (Pin 18):
Encode Complement Input. Conversion Connecting MODE to VDD selects 2’s complement output starts on the negative edge. Bypass to ground with 0.1µF format and turns the clock duty cycle stabilizer off. ceramic for single-ended encode signal.
SENSE (Pin 59):
Reference Programming Pin. Connecting
SHDN (Pin 19):
Shutdown Mode Selection Pin. Connecting SENSE to VCM selects the internal reference and a ±0.5V SHDN to GND and OE to GND results in normal operation input range. Connecting SENSE to VDD selects the internal with the outputs enabled. Connecting SHDN to GND and reference and a ±1V input range. An external reference OE to VDD results in normal operation with the outputs at greater than 0.5V and less than 1V applied to SENSE high impedance. Connecting SHDN to VDD and OE to GND selects an input range of ±VSENSE. ±1V is the largest valid results in nap mode with the outputs at high impedance. input range. Connecting SHDN to VDD and OE to VDD results in sleep
VCM (Pin 60):
1.25V Output and Input Common Mode mode with the outputs at high impedance. Bias. Bypass to ground with 2.2µF ceramic chip capacitor.
OE (Pin 20):
Output Enable Pin. Refer to SHDN pin function.
GND (Exposed Pad) (Pin 65):
ADC Power Ground. The
DNC (Pins 21, 22, 23, 24):
Do not connect these pins. exposed pad on the bottom of the package needs to be
D0–/D0+ to D9–/D9+ (Pins 27, 28, 29, 30, 31, 32, 37,
soldered to ground.
38, 39, 40, 43, 44, 45, 46, 47, 48, 51, 52, 53, 54):
LVDS Digital Outputs. All LVDS outputs require differential 100Ω termination resistors at the LVDS receiver. D9–/D9+ is the MSB. 224210fd 10 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagrams Applications Information Package Description Revision History Related Parts
pin FuncTions (LVDS Mode) AIN+ (Pins 1, 2):
Positive Differential Analog Input.
OGND (Pins 25, 33, 41, 50):
Output Driver Ground.
AIN– (Pins 3, 4):
Negative Differential Analog Input.
OVDD (Pins 26, 34, 42, 49):
Positive Supply for the Out-
REFHA (Pins 5, 6):
ADC High Reference. Bypass to put Drivers. Bypass to ground with 0.1µF ceramic chip Pins 7, 8 with 0.1µF ceramic chip capacitor, to Pins 11, capacitor. 12 with a 2.2µF ceramic capacitor and to ground with 1µF
CLKOUT–/CLKOUT+ (Pins 35 to 36):
LVDS Data Valid ceramic capacitor. Output. Latch data on rising edge of CLKOUT–, falling
REFLB (Pins 7, 8):
ADC Low Reference. Bypass to Pins edge of CLKOUT+. 5, 6 with 0.1µF ceramic chip capacitor. Do not connect to
OF–/OF+ (Pins 55 to 56):
LVDS Over/Under Flow Output. Pins 11, 12. High when an over or under flow has occurred.
REFHB (Pins 9, 10):
ADC High Reference. Bypass to
LVDS (Pin 57):
Output Mode Selection Pin. Connecting Pins 11, 12 with 0.1µF ceramic chip capacitor. Do not LVDS to 0V selects full rate CMOS mode. Connecting LVDS connect to Pins 5, 6. to 1/3VDD selects demux CMOS mode with simultaneous
REFLA (Pins 11, 12):
ADC Low Reference. Bypass to update. Connecting LVDS to 2/3VDD selects demux CMOS Pins 9, 10 with 0.1µF ceramic chip capacitor, to Pins 5, mode with interleaved update. Connecting LVDS to VDD 6 with a 2.2µF ceramic capacitor and to ground with 1µF selects LVDS mode. ceramic capacitor.
MODE (Pin 58):
Output Format and Clock Duty Cycle
V
Stabilizer Selection Pin. Connecting MODE to 0V selects
DD (Pins 13, 14, 15, 62, 63):
2.5V Supply. Bypass to GND with 0.1µF ceramic chip capacitors. offset binary output format and turns the clock duty cycle stabilizer off. Connecting MODE to 1/3V
GND (Pins 16, 61, 64):
ADC Power Ground. DD selects offset binary output format and turns the clock duty cycle stabilizer
ENC+ (Pin 17):
Encode Input. Conversion starts on the on. Connecting MODE to 2/3VDD selects 2’s complement positive edge. output format and turns the clock duty cycle stabilizer on.
ENC– (Pin 18):
Encode Complement Input. Conversion Connecting MODE to VDD selects 2’s complement output starts on the negative edge. Bypass to ground with 0.1µF format and turns the clock duty cycle stabilizer off. ceramic for single-ended encode signal.
SENSE (Pin 59):
Reference Programming Pin. Connecting
SHDN (Pin 19):
Shutdown Mode Selection Pin. Connecting SENSE to VCM selects the internal reference and a ±0.5V SHDN to GND and OE to GND results in normal operation input range. Connecting SENSE to VDD selects the internal with the outputs enabled. Connecting SHDN to GND and reference and a ±1V input range. An external reference OE to VDD results in normal operation with the outputs at greater than 0.5V and less than 1V applied to SENSE high impedance. Connecting SHDN to VDD and OE to GND selects an input range of ±VSENSE. ±1V is the largest valid results in nap mode with the outputs at high impedance. input range. Connecting SHDN to VDD and OE to VDD results in sleep
VCM (Pin 60):
1.25V Output and Input Common Mode mode with the outputs at high impedance. Bias. Bypass to ground with 2.2µF ceramic chip capacitor.
OE (Pin 20):
Output Enable Pin. Refer to SHDN pin function.
GND (Exposed Pad) (Pin 65):
ADC Power Ground. The
DNC (Pins 21, 22, 23, 24):
Do not connect these pins. exposed pad on the bottom of the package needs to be
D0–/D0+ to D9–/D9+ (Pins 27, 28, 29, 30, 31, 32, 37,
soldered to ground.
38, 39, 40, 43, 44, 45, 46, 47, 48, 51, 52, 53, 54):
LVDS Digital Outputs. All LVDS outputs require differential 100Ω termination resistors at the LVDS receiver. D9–/D9+ is the MSB. 224210fd 10 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagrams Applications Information Package Description Revision History Related Parts
