Datasheet LTC2268-12, LTC2267-12, LTC2266-12 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | 12-Bit, 125Msps Low Power Dual ADCs |
| Pages / Page | 32 / 5 — DigiTal inpuTs anD ouTpuTs. The. denotes the specifications which apply … |
| File Format / Size | PDF / 1.1 Mb |
| Document Language | English |
DigiTal inpuTs anD ouTpuTs. The. denotes the specifications which apply over the full operating
Model Line for this Datasheet
- LTC2266CUJ-12#PBF LTC2266CUJ-12#PBF LTC2266CUJ-12#TRPBF LTC2266CUJ-12#TRPBF LTC2266IUJ-12#PBF LTC2266IUJ-12#PBF LTC2266IUJ-12#TRPBF LTC2266IUJ-12#TRPBF
Text Version of Document
LTC2268-12/ LTC2267-12/LTC2266-12
DigiTal inpuTs anD ouTpuTs The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)
VIH High Level Input Voltage VDD =1.8V l 1.3 V VIL Low Level Input Voltage VDD =1.8V l 0.6 V IIN Input Current VIN = 0V to 3.6V l –10 10 µA CIN Input Capacitance 3 pF
SDO OUTPUT (Serial Programming Mode. Open Drain Output. Requires 2kΩ Pull-Up Resistor if SDO is Used)
ROL Logic Low Output Resistance to GND VDD =1.8V, SDO = 0V 200 Ω IOH Logic High Output Leakage Current SDO = 0V to 3.6V l –10 10 µA COUT Output Capacitance 3 pF
DIGITAL DATA OUTPUTS
VOD Differential Output Voltage 100Ω Differential Load, 3.5mA Mode l 247 350 454 mV 100Ω Differential Load, 1.75mA Mode l 125 175 250 mV VOS Common Mode Output Voltage 100Ω Differential Load, 3.5mA Mode l 1.125 1.25 1.375 V 100Ω Differential Load, 1.75mA Mode l 1.125 1.25 1.375 V RTERM On-Chip Termination Resistance Termination Enabled, OVDD =1.8V 100 Ω
poWer reQuireMenTs The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) LTC2268-12 LTC2267-12 LTC2266-12 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V IVDD Analog Supply Current Sine Wave Input l 146 165 116 129 96 109 mA IOVDD Digital Supply Current 2-Lane Mode, 1.75mA Mode l 16 20 16 19 15 18 mA 2-Lane Mode, 3.5mA Mode l 30 34 29 33 29 32 mA PDISS Power Dissipation 2-Lane Mode, 1.75mA Mode l 292 333 238 266 200 229 mW 2-Lane Mode, 3.5mA Mode l 317 358 261 292 225 254 mW PSLEEP Sleep Mode Power 1 1 1 mW PNAP Nap Mode Power 70 70 70 mW PDIFFCLK Power Increase with Differential Encode Mode Enabled 20 20 20 mW (No Increase for Sleep Mode)
TiMing characTerisTics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) LTC2268-12 LTC2267-12 LTC2266-12 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
fS Sampling Frequency (Notes 10, 11) l 5 125 5 105 5 80 MHz tENCL ENC Low Time (Note 8) Duty Cycle Stabilizer Off l 3.8 4 100 4.52 4.76 100 5.93 6.25 100 ns Duty Cycle Stabilizer On l 2 4 100 2 4.76 100 2 6.25 100 ns tENCH Analog Supply Current Duty Cycle Stabilizer Off l 3.8 4 100 4.52 4.76 100 5.93 6.25 100 ns Duty Cycle Stabilizer On l 2 4 100 2 4.76 100 2 6.25 100 ns tAP Sample-and-Hold 0 0 0 ns Acquisition Delay Time 22687612fa 5 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Digital Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Electrical Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts
DigiTal inpuTs anD ouTpuTs The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)
VIH High Level Input Voltage VDD =1.8V l 1.3 V VIL Low Level Input Voltage VDD =1.8V l 0.6 V IIN Input Current VIN = 0V to 3.6V l –10 10 µA CIN Input Capacitance 3 pF
SDO OUTPUT (Serial Programming Mode. Open Drain Output. Requires 2kΩ Pull-Up Resistor if SDO is Used)
ROL Logic Low Output Resistance to GND VDD =1.8V, SDO = 0V 200 Ω IOH Logic High Output Leakage Current SDO = 0V to 3.6V l –10 10 µA COUT Output Capacitance 3 pF
DIGITAL DATA OUTPUTS
VOD Differential Output Voltage 100Ω Differential Load, 3.5mA Mode l 247 350 454 mV 100Ω Differential Load, 1.75mA Mode l 125 175 250 mV VOS Common Mode Output Voltage 100Ω Differential Load, 3.5mA Mode l 1.125 1.25 1.375 V 100Ω Differential Load, 1.75mA Mode l 1.125 1.25 1.375 V RTERM On-Chip Termination Resistance Termination Enabled, OVDD =1.8V 100 Ω
poWer reQuireMenTs The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) LTC2268-12 LTC2267-12 LTC2266-12 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V IVDD Analog Supply Current Sine Wave Input l 146 165 116 129 96 109 mA IOVDD Digital Supply Current 2-Lane Mode, 1.75mA Mode l 16 20 16 19 15 18 mA 2-Lane Mode, 3.5mA Mode l 30 34 29 33 29 32 mA PDISS Power Dissipation 2-Lane Mode, 1.75mA Mode l 292 333 238 266 200 229 mW 2-Lane Mode, 3.5mA Mode l 317 358 261 292 225 254 mW PSLEEP Sleep Mode Power 1 1 1 mW PNAP Nap Mode Power 70 70 70 mW PDIFFCLK Power Increase with Differential Encode Mode Enabled 20 20 20 mW (No Increase for Sleep Mode)
TiMing characTerisTics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) LTC2268-12 LTC2267-12 LTC2266-12 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
fS Sampling Frequency (Notes 10, 11) l 5 125 5 105 5 80 MHz tENCL ENC Low Time (Note 8) Duty Cycle Stabilizer Off l 3.8 4 100 4.52 4.76 100 5.93 6.25 100 ns Duty Cycle Stabilizer On l 2 4 100 2 4.76 100 2 6.25 100 ns tENCH Analog Supply Current Duty Cycle Stabilizer Off l 3.8 4 100 4.52 4.76 100 5.93 6.25 100 ns Duty Cycle Stabilizer On l 2 4 100 2 4.76 100 2 6.25 100 ns tAP Sample-and-Hold 0 0 0 ns Acquisition Delay Time 22687612fa 5 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Digital Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Electrical Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts
