Datasheet LTC2268-12, LTC2267-12, LTC2266-12 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | 12-Bit, 125Msps Low Power Dual ADCs |
| Pages / Page | 32 / 9 — TiMing DiagraMs. 1-Lane Output Mode, 14-Bit Serialization. 1-Lane Output … |
| File Format / Size | PDF / 1.1 Mb |
| Document Language | English |
TiMing DiagraMs. 1-Lane Output Mode, 14-Bit Serialization. 1-Lane Output Mode, 12-Bit Serialization
Model Line for this Datasheet
- LTC2266CUJ-12#PBF LTC2266CUJ-12#PBF LTC2266CUJ-12#TRPBF LTC2266CUJ-12#TRPBF LTC2266IUJ-12#PBF LTC2266IUJ-12#PBF LTC2266IUJ-12#TRPBF LTC2266IUJ-12#TRPBF
Text Version of Document
LTC2268-12/ LTC2267-12/LTC2266-12
TiMing DiagraMs 1-Lane Output Mode, 14-Bit Serialization
tAP N + 1 ANALOG INPUT N tENCH tENCL ENC– ENC+ tSER DCO– DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUT#A– D1 D0 DX* DY* D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DX* DY* D11 D10 D9 D8 OUT#A+ SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 226812 TD05 OUT#B+, OUT#B– ARE DISABLED *DX AND DY ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION DX AND DY ARE SET TO LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.
1-Lane Output Mode, 12-Bit Serialization
tAP ANALOG N + 1 INPUT N tENCH tENCL ENC– ENC+ tSER DCO– DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUT#A– D3 D2 D1 D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 OUT#A+ SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 226812 TD06 OUT#B+, OUT#B– ARE DISABLED 22687612fa 9 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Digital Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Electrical Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts
TiMing DiagraMs 1-Lane Output Mode, 14-Bit Serialization
tAP N + 1 ANALOG INPUT N tENCH tENCL ENC– ENC+ tSER DCO– DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUT#A– D1 D0 DX* DY* D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DX* DY* D11 D10 D9 D8 OUT#A+ SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 226812 TD05 OUT#B+, OUT#B– ARE DISABLED *DX AND DY ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION DX AND DY ARE SET TO LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.
1-Lane Output Mode, 12-Bit Serialization
tAP ANALOG N + 1 INPUT N tENCH tENCL ENC– ENC+ tSER DCO– DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUT#A– D3 D2 D1 D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 OUT#A+ SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 226812 TD06 OUT#B+, OUT#B– ARE DISABLED 22687612fa 9 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Digital Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Electrical Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts
