Datasheet LTC2377-20 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 20-Bit, 500ksps, Low Power SAR ADC with 0.5ppm INL |
| Pages / Page | 30 / 10 — TIMING DIAGRAM. Conversion Timing Using the Serial Interface. … |
| File Format / Size | PDF / 1.0 Mb |
| Document Language | English |
TIMING DIAGRAM. Conversion Timing Using the Serial Interface. APPLICATIONS INFORMATION. OVERVIEW. CONVERTER OPERATION
Model Line for this Datasheet
- LTC2377CDE-20#PBF LTC2377CDE-20#PBF LTC2377CDE-20#TRPBF LTC2377CDE-20#TRPBF LTC2377CMS-20#PBF LTC2377CMS-20#PBF LTC2377CMS-20#TRPBF LTC2377CMS-20#TRPBF LTC2377IDE-20#PBF LTC2377IDE-20#PBF LTC2377IDE-20#TRPBF LTC2377IDE-20#TRPBF LTC2377IMS-20#PBF LTC2377IMS-20#PBF LTC2377IMS-20#TRPBF LTC2377IMS-20#TRPBF
Text Version of Document
LTC2377-20
TIMING DIAGRAM Conversion Timing Using the Serial Interface
CHAIN, RDL/SDI = 0 CNV CONVERT POWER-DOWN BUSY HOLD ACQUIRE SCK D19 D18 D17 D2 D1 D0 SDO 237720 TD01
APPLICATIONS INFORMATION OVERVIEW CONVERTER OPERATION
The LTC2377-20 is a low noise, low power, high speed The LTC2377-20 operates in two phases. During the ac- 20-bit successive approximation register (SAR) ADC. quisition phase, the charge redistribution capacitor D/A Operating from a single 2.5V supply, the LTC2377-20 converter (CDAC) is connected to the IN+ and IN– pins supports a large and flexible ±VREF fully differential input to sample the differential analog input voltage. A rising range with VREF ranging from 2.5V to 5.1V, making it ideal edge on the CNV pin initiates a conversion. During the for high performance applications which require a wide conversion phase, the 20-bit CDAC is sequenced through a dynamic range. The LTC2377-20 achieves ±2ppm INL successive approximation algorithm, effectively comparing maximum, no missing codes at 20 bits and 104dB SNR. the sampled input with binary-weighted fractions of the Fast 500ksps throughput with no cycle latency makes reference voltage (e.g. VREF/2, VREF/4 … VREF/1048576) the LTC2377-20 ideally suited for a wide variety of high using the differential comparator. At the end of conversion, speed applications. An internal oscillator sets the con- the CDAC output approximates the sampled analog input. version time, easing external timing considerations. The The ADC control logic then prepares the 20-bit digital LTC2377-20 dissipates only 10.5mW at 500ksps, while output code for serial transfer. an auto power-down feature is provided to further reduce power dissipation during inactive periods.
TRANSFER FUNCTION
The LTC2377-20 features a unique digital gain compres- The LTC2377-20 digitizes the full-scale voltage of 2 × REF sion (DGC) function, which eliminates the driver amplifier’s into 220 levels, resulting in an LSB size of 9.5µV with negative supply while preserving the full resolution of the REF = 5V. Note that 1 LSB at 20 bits is approximately ADC. When enabled, the ADC performs a digital scaling 1ppm. The ideal transfer function is shown in Figure 2. function that maps zero-scale code from 0V to 0.1 • VREF The output data is in 2’s complement format. and full-scale code from VREF to 0.9 • VREF. For a typical reference voltage of 5V, the full-scale input range is now
ANALOG INPUT
0.5V to 4.5V, which provides adequate headroom for powering the driving amplifier from a single 5.5V supply. The analog inputs of the LTC2377-20 are fully differential in order to maximize the signal swing that can be digitized. The analog inputs can be modeled by the equivalent circuit 237720fb 10 For more information www.linear.com/LTC2377-20 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics converter Characteristics Dynamic Accuracy Reference Input Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Board Layout Package Description Revision History Typical Application Related Parts
TIMING DIAGRAM Conversion Timing Using the Serial Interface
CHAIN, RDL/SDI = 0 CNV CONVERT POWER-DOWN BUSY HOLD ACQUIRE SCK D19 D18 D17 D2 D1 D0 SDO 237720 TD01
APPLICATIONS INFORMATION OVERVIEW CONVERTER OPERATION
The LTC2377-20 is a low noise, low power, high speed The LTC2377-20 operates in two phases. During the ac- 20-bit successive approximation register (SAR) ADC. quisition phase, the charge redistribution capacitor D/A Operating from a single 2.5V supply, the LTC2377-20 converter (CDAC) is connected to the IN+ and IN– pins supports a large and flexible ±VREF fully differential input to sample the differential analog input voltage. A rising range with VREF ranging from 2.5V to 5.1V, making it ideal edge on the CNV pin initiates a conversion. During the for high performance applications which require a wide conversion phase, the 20-bit CDAC is sequenced through a dynamic range. The LTC2377-20 achieves ±2ppm INL successive approximation algorithm, effectively comparing maximum, no missing codes at 20 bits and 104dB SNR. the sampled input with binary-weighted fractions of the Fast 500ksps throughput with no cycle latency makes reference voltage (e.g. VREF/2, VREF/4 … VREF/1048576) the LTC2377-20 ideally suited for a wide variety of high using the differential comparator. At the end of conversion, speed applications. An internal oscillator sets the con- the CDAC output approximates the sampled analog input. version time, easing external timing considerations. The The ADC control logic then prepares the 20-bit digital LTC2377-20 dissipates only 10.5mW at 500ksps, while output code for serial transfer. an auto power-down feature is provided to further reduce power dissipation during inactive periods.
TRANSFER FUNCTION
The LTC2377-20 features a unique digital gain compres- The LTC2377-20 digitizes the full-scale voltage of 2 × REF sion (DGC) function, which eliminates the driver amplifier’s into 220 levels, resulting in an LSB size of 9.5µV with negative supply while preserving the full resolution of the REF = 5V. Note that 1 LSB at 20 bits is approximately ADC. When enabled, the ADC performs a digital scaling 1ppm. The ideal transfer function is shown in Figure 2. function that maps zero-scale code from 0V to 0.1 • VREF The output data is in 2’s complement format. and full-scale code from VREF to 0.9 • VREF. For a typical reference voltage of 5V, the full-scale input range is now
ANALOG INPUT
0.5V to 4.5V, which provides adequate headroom for powering the driving amplifier from a single 5.5V supply. The analog inputs of the LTC2377-20 are fully differential in order to maximize the signal swing that can be digitized. The analog inputs can be modeled by the equivalent circuit 237720fb 10 For more information www.linear.com/LTC2377-20 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics converter Characteristics Dynamic Accuracy Reference Input Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Board Layout Package Description Revision History Typical Application Related Parts
