Datasheet LTC2380-16 (Analog Devices) - 10

LTC2380-16
APPLICATIONS INFORMATION OVERVIEW TRANSFER FUNCTION
The LTC2380-16 is a low noise, low power, high speed 16-bit The LTC2380-16 digitizes the full-scale voltage of 2 × REF successive approximation register (SAR) ADC. Operating into 216 levels, resulting in an LSB size of 152µV with from a single 2.5V supply, the LTC2380-16 supports a REF = 5V. The ideal transfer function is shown in Figure 2. large and flexible ±VREF fully differential input range with The output data is in 2’s complement format. VREF ranging from 2.5V to 5.1V, making it ideal for high performance applications which require a wide dynamic range. The LTC2380-16 achieves ±0.6LSB INL max, no 011...111 011...110 BIPOLAR missing codes at 16 bits and 96.2dB SNR. ZERO Fast 2Msps throughput with no cycle latency makes the 000...001 LTC2380-16 ideally suited for a wide variety of high speed 000...000 111...111 applications. An internal oscillator sets the conversion time, 111...110 easing external timing considerations. The LTC2380-16 dissipates only 19mW at 2Msps, while an auto power-down 100...001 FSR = +FS – –FS feature is provided to further reduce power dissipation OUTPUT CODE (TWO’S COMPLEMENT) 100...000 1LSB = FSR/65536 during inactive periods. –FSR/2 –1 0V 1 FSR/2 – 1LSB LSB The LTC2380-16 features a unique digital gain compres- LSB INPUT VOLTAGE (V) sion (DGC) function, which eliminates the driver amplifier’s 238016 F02
Figure 2. LTC2380-16 Transfer Function
negative supply while preserving the full resolution of the ADC. When enabled, the ADC performs a digital scaling
ANALOG INPUT
function that maps zero-scale code from 0V to 0.1 • VREF The analog inputs of the LTC2380-16 are fully differential and full-scale code from VREF to 0.9 • VREF. For a typical in order to maximize the signal swing that can be digitized. reference voltage of 5V, the full-scale input range is now The analog inputs can be modeled by the equivalent circuit 0.5V to 4.5V, which provides adequate headroom for shown in Figure 3. The diodes at the input provide ESD powering the driving amplifier from a single 5.5V supply. protection. In the acquisition phase, each input sees ap- proximately 45pF (CIN) from the sampling CDAC in series
CONVERTER OPERATION
with 40Ω (RON) from the on-resistance of the sampling switch. Any unwanted signal that is common to both The LTC2380-16 operates in two phases. During the ac- inputs will be reduced by the common mode rejection of quisition phase, the charge redistribution capacitor D/A the ADC. The inputs draw a current spike while charging converter (CDAC) is connected to the IN+ and IN– pins the C to sample the differential analog input voltage. A rising IN capacitors during acquisition. During conversion, the analog inputs draw only a small leakage current. edge on the CNV pin initiates a conversion. During the conversion phase, the 16-bit CDAC is sequenced through a REF successive approximation algorithm, effectively comparing C R IN ON 45pF the sampled input with binary-weighted fractions of the 40Ω IN+ reference voltage (e.g. VREF/2, VREF/4 … VREF/65536) using the differential comparator. At the end of conversion, the BIAS CDAC output approximates the sampled analog input. The REF VOLTAGE CIN ADC control logic then prepares the 16-bit digital output RON 45pF 40Ω code for serial transfer. IN– 238016 F03
Figure 3. The Equivalent Circuit for the Differential Analog Input of the LTC2380-16
238016fb 10 For more information www.linear.com/LTC2380-16 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Converter Characteristics Dynamic Accuracy Reference Input Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Board Layout Package Description Typical Application Related Parts