Datasheet LTC2404, LTC2408 (Analog Devices) - 28
| Manufacturer | Analog Devices |
| Description | 4-/8-Channel 24-Bit µPower No Latency ∆∑TM ADCs |
| Pages / Page | 36 / 28 — APPLICATIONS INFORMATION. Figure 25. Using the Multiplexer to Produce … |
| File Format / Size | PDF / 374 Kb |
| Document Language | English |
APPLICATIONS INFORMATION. Figure 25. Using the Multiplexer to Produce Programmable Gains of 1 to 128
Model Line for this Datasheet
Text Version of Document
LTC2404/LTC2408
U U W U APPLICATIONS INFORMATION
5V 3 AV = 1, 2, 4...128 VIN + 6 LTC1050 2 – 5V 0.1V TO VCC 7 4 3 2, 8 10k 1µF 2 MUXOUT ADCIN VREF VCC 9 CH0 20k 10k 4 10 CH1 23 CSADC 11 CH2 20 CSMUX 20k 10k 8 12 CH3 25 8-CHANNEL SCK 24-BIT 13 CH4 19 20k 10k MUX ∆Σ ADC CLK 16 14 CH5 21 DIN 15 CH6 24 20k 10k SDO 32 17 CH7 LTC2408 VCC 20k 10k 26 64 GND FO 2404/08 F25 1, 5, 6, 16, 18, 22, 27, 28 20k 10k 128 20k 10k
Figure 25. Using the Multiplexer to Produce Programmable Gains of 1 to 128
5V OPTIONAL BANDWIDTH 3 7 LIMIT + 6 LTC1050 2 C1 MAY BE REQUIRED BY OTHER – R4 0.022µF 4 AMPLIFIERS (IS REQUIRED BY R3 5K BIPOLAR AMPLIFIERS) 200k R1 5.1k R2 5.1K C2 OPTIONAL GAIN 5V AND ROLL-OFF 7 4 3 2, 8 10µF MUXOUT ADCIN VREF VCC 9 CH0 10 CH1 23 CSADC 11 CH2 20 CSMUX 12 CH3 25 SCK ANALOG 8-CHANNEL 24-BIT 13 CH4 19 INPUTS MUX ∆Σ ADC CLK 14 CH5 21 DIN 15 CH6 24 SDO 17 CH7 LTC2408 VCC 26 GND FO 2404/08 F26 1, 5, 6, 16, 18, 22, 27, 28
Figure 26. Inserting Gain Between the Multiplexer and the ADC Input
28
U U W U APPLICATIONS INFORMATION
5V 3 AV = 1, 2, 4...128 VIN + 6 LTC1050 2 – 5V 0.1V TO VCC 7 4 3 2, 8 10k 1µF 2 MUXOUT ADCIN VREF VCC 9 CH0 20k 10k 4 10 CH1 23 CSADC 11 CH2 20 CSMUX 20k 10k 8 12 CH3 25 8-CHANNEL SCK 24-BIT 13 CH4 19 20k 10k MUX ∆Σ ADC CLK 16 14 CH5 21 DIN 15 CH6 24 20k 10k SDO 32 17 CH7 LTC2408 VCC 20k 10k 26 64 GND FO 2404/08 F25 1, 5, 6, 16, 18, 22, 27, 28 20k 10k 128 20k 10k
Figure 25. Using the Multiplexer to Produce Programmable Gains of 1 to 128
5V OPTIONAL BANDWIDTH 3 7 LIMIT + 6 LTC1050 2 C1 MAY BE REQUIRED BY OTHER – R4 0.022µF 4 AMPLIFIERS (IS REQUIRED BY R3 5K BIPOLAR AMPLIFIERS) 200k R1 5.1k R2 5.1K C2 OPTIONAL GAIN 5V AND ROLL-OFF 7 4 3 2, 8 10µF MUXOUT ADCIN VREF VCC 9 CH0 10 CH1 23 CSADC 11 CH2 20 CSMUX 12 CH3 25 SCK ANALOG 8-CHANNEL 24-BIT 13 CH4 19 INPUTS MUX ∆Σ ADC CLK 14 CH5 21 DIN 15 CH6 24 SDO 17 CH7 LTC2408 VCC 26 GND FO 2404/08 F26 1, 5, 6, 16, 18, 22, 27, 28
Figure 26. Inserting Gain Between the Multiplexer and the ADC Input
28
