Datasheet LTC2452 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Ultra-Tiny, Differential, 16-Bit ΔΣ ADC with SPI Interface |
| Pages / Page | 22 / 10 — applicaTions inForMaTion. Serial Clock Idle-High (CPOL = 1) Examples. … |
| File Format / Size | PDF / 491 Kb |
| Document Language | English |
applicaTions inForMaTion. Serial Clock Idle-High (CPOL = 1) Examples. Serial Clock Idle-Low (CPOL = 0) Examples
Model Line for this Datasheet
- LTC2452CDDB#PBF LTC2452CDDB#TRMPBF LTC2452CDDB#TRMPBF LTC2452CDDB#TRPBF LTC2452CDDB#TRPBF LTC2452CTS8#PBF LTC2452CTS8#TRMPBF LTC2452CTS8#TRMPBF LTC2452CTS8#TRPBF LTC2452CTS8#TRPBF LTC2452IDDB#PBF LTC2452IDDB#TRMPBF LTC2452IDDB#TRMPBF LTC2452IDDB#TRPBF LTC2452IDDB#TRPBF LTC2452ITS8#PBF LTC2452ITS8#TRMPBF LTC2452ITS8#TRMPBF LTC2452ITS8#TRPBF LTC2452ITS8#TRPBF
Text Version of Document
LTC2452
applicaTions inForMaTion
2) After the 16th bit is read, the user can choose one of Pulling CS LOW while SCK is HIGH tests whether or not two ways to begin a new conversion. First, one can the chip is in the CONVERT state. While in the CONVERT pull CS high (CS = ↑). Second, one can use a high-low state, SDO is HIGH while CS is LOW. In the SLEEP state, transition on SCK (SCK = ↓). SDO is LOW while CS is LOW. These tests are not required 3) At any time during the Data Output state, pulling CS operational steps but may be useful for some applications. high (CS = ↑) causes the part to leave the I/O state, When the data is available, the user applies 16 clock cycles abort the output and begin a new conversion. to transfer the result. The CS rising edge is then used to 4) When SCK = HIGH, it is possible to monitor the conver- initiate a new conversion. sion status by pulling CS low and watching for SDO to The operation example of Figure 7 is identical to that of go low. This feature is available only in the idle-high Figure 6, except the new conversion cycle is triggered by (CPOL = 1) mode. the falling edge of the serial clock (SCK). A 17th clock pulse is used to trigger a new conversion cycle.
Serial Clock Idle-High (CPOL = 1) Examples
In Figure 6, following a conversion cycle the LTC2452
Serial Clock Idle-Low (CPOL = 0) Examples
automatically enters the low power sleep mode. The user In Figure 8, following a conversion cycle the LTC2452 can monitor the conversion status at convenient intervals automatically enters the low-power sleep state. The user using CS and SDO. determines data availability (and the end of conversion) CS SD0 D15 D14 D13 D12 D2 D1 D0 SCK clk1 clk2 clk3 clk4 clk15 clk16 CONVERT SLEEP DATA OUTPUT CONVERT 2452 F06
Figure 6. Idle-High (CPOL = 1) Serial Clock Operation Example. The Rising Edge of CS Starts a New Conversion
CS SD0 D15 D14 D13 D12 D2 D1 D0 SCK clk1 clk2 clk3 clk4 clk15 clk16 clk17 CONVERT SLEEP DATA OUTPUT CONVERT 2452 F07
Figure 7. Idle-High (CPOL = 1) Clock Operation Example. A 17th Clock Pulse is Used to Trigger a New Conversion Cycle
2452fd 10 For more information www.linear.com/LTC2452
applicaTions inForMaTion
2) After the 16th bit is read, the user can choose one of Pulling CS LOW while SCK is HIGH tests whether or not two ways to begin a new conversion. First, one can the chip is in the CONVERT state. While in the CONVERT pull CS high (CS = ↑). Second, one can use a high-low state, SDO is HIGH while CS is LOW. In the SLEEP state, transition on SCK (SCK = ↓). SDO is LOW while CS is LOW. These tests are not required 3) At any time during the Data Output state, pulling CS operational steps but may be useful for some applications. high (CS = ↑) causes the part to leave the I/O state, When the data is available, the user applies 16 clock cycles abort the output and begin a new conversion. to transfer the result. The CS rising edge is then used to 4) When SCK = HIGH, it is possible to monitor the conver- initiate a new conversion. sion status by pulling CS low and watching for SDO to The operation example of Figure 7 is identical to that of go low. This feature is available only in the idle-high Figure 6, except the new conversion cycle is triggered by (CPOL = 1) mode. the falling edge of the serial clock (SCK). A 17th clock pulse is used to trigger a new conversion cycle.
Serial Clock Idle-High (CPOL = 1) Examples
In Figure 6, following a conversion cycle the LTC2452
Serial Clock Idle-Low (CPOL = 0) Examples
automatically enters the low power sleep mode. The user In Figure 8, following a conversion cycle the LTC2452 can monitor the conversion status at convenient intervals automatically enters the low-power sleep state. The user using CS and SDO. determines data availability (and the end of conversion) CS SD0 D15 D14 D13 D12 D2 D1 D0 SCK clk1 clk2 clk3 clk4 clk15 clk16 CONVERT SLEEP DATA OUTPUT CONVERT 2452 F06
Figure 6. Idle-High (CPOL = 1) Serial Clock Operation Example. The Rising Edge of CS Starts a New Conversion
CS SD0 D15 D14 D13 D12 D2 D1 D0 SCK clk1 clk2 clk3 clk4 clk15 clk16 clk17 CONVERT SLEEP DATA OUTPUT CONVERT 2452 F07
Figure 7. Idle-High (CPOL = 1) Clock Operation Example. A 17th Clock Pulse is Used to Trigger a New Conversion Cycle
2452fd 10 For more information www.linear.com/LTC2452
