Datasheet LTC2482 (Analog Devices) - 8

ManufacturerAnalog Devices
Description16-Bit ΔΣ ADC with Easy Drive Input Current Cancellation
Pages / Page32 / 8 — PIN FUNCTIONS GND (Pin 1):. GND (Pin 8):. VCC (Pin 2):. SCK (Pin 9):. …
File Format / SizePDF / 325 Kb
Document LanguageEnglish

PIN FUNCTIONS GND (Pin 1):. GND (Pin 8):. VCC (Pin 2):. SCK (Pin 9):. VREF (Pin 3):. IN+ (Pin 4), IN– (Pin 5):. O (Pin 10):

PIN FUNCTIONS GND (Pin 1): GND (Pin 8): VCC (Pin 2): SCK (Pin 9): VREF (Pin 3): IN+ (Pin 4), IN– (Pin 5): O (Pin 10):

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Text Version of Document

LTC2482
PIN FUNCTIONS GND (Pin 1):
Ground. This pin should be tied to ground;
GND (Pin 8):
Ground. Shared pin for analog ground, digital however, in order to remain pin compatible with the ground and reference ground. Should be connected directly LTC2480/LTC2484, this pin may be driven high or low. to a ground plane through a minimum impedance.
VCC (Pin 2):
Positive Supply Voltage. Bypass to GND (Pin 8)
SCK (Pin 9):
Bidirectional Digital Clock Pin. In internal serial with a 1μF tantalum capacitor in parallel with 0.1μF ceramic clock operation mode, SCK is used as the digital output for capacitor as close to the part as possible. the internal serial interface clock during the data output period. In external serial clock operation mode, SCK is used
VREF (Pin 3):
Positive Reference Input. The voltage on as the digital input for the external serial interface clock this pin can have any value between 0.1V and VCC. The during the data output period. A weak internal pull-up is negative reference input is GND (Pin 8). automatically activated in internal serial clock operation
IN+ (Pin 4), IN– (Pin 5):
Differential Analog Inputs. The mode. The serial clock operation mode is determined by voltage on these pins can have any value between GND the logic level applied to the SCK pin at power up or during – 0.3V and VCC + 0.3V. Within these limits the converter the most recent falling edge of CS. bipolar input range (VIN = IN+ – IN–) extends from –0.5 •
f
V
O (Pin 10):
Frequency Control Pin. Digital input that REF to 0.5 • VREF . Outside this input range the converter controls the conversion clock. When f produces unique overrange and underrange output codes. O is connected to GND the converter uses its internal oscillator running at
CS (Pin 6):
Active Low Chip Select. A low on this pin 307.2kHz. The conversion clock may also be overridden by enables the digital input/output and wakes up the ADC. driving the fO pin with an external clock in order to change Following each conversion the ADC automatically enters the output rate or the digital fi lter rejection null. the sleep mode and remains in this low power state as
Exposed Pad (Pin 11):
This pin is ground and should be long as CS is high. A low-to-high transition on CS during soldered to the PCB, GND plane. For prototyping purposes the data output transfer aborts the data transfer and starts this pin may remain fl oating. a new conversion.
SDO (Pin 7):
Three-State Digital Output. During the data output period, this pin is used as the serial data output. When the chip select, CS, is high (CS = VCC), the SDO pin is in a high impedance state. During the conversion and sleep periods, this pin is used as the conversion status output. The conversion status can be observed by pulling CS low. 2482fc 8