Datasheet LTM9013 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 300MHz Wideband Receiver |
| Pages / Page | 38 / 10 — pin FuncTions Control Pins. SCK (Pin J11):. EN (Pin B8):. EIP2 (Pin D6):. … |
| File Format / Size | PDF / 978 Kb |
| Document Language | English |
pin FuncTions Control Pins. SCK (Pin J11):. EN (Pin B8):. EIP2 (Pin D6):. CS (Pin K10):. NC1, NC2, NC3 (Pins C6, C9, D9):. EN_I
Model Line for this Datasheet
Text Version of Document
LTM9013
pin FuncTions Control Pins SCK (Pin J11):
Serial Interface Clock Input. In serial
EN (Pin B8):
Demodulator Enable Pin. If EN = high (the programming mode (PAR/SER = GND), SCK is the serial input voltage is higher than 2.0V), the demodulator is en- interface clock input. In the parallel programming mode abled. If EN = low (the input voltage is less than 1.0V), it (PAR/SER = VDD), SCK can be used to place the part in the is disabled. If the enable function is not needed, then this low power sleep mode (see Table 4). SCK can be driven pin should be tied to V with 1.8V to 3.3V logic. CC1.
EIP2 (Pin D6):
Demodulator IP2 Adjust Enable Pin. Pin is
CS (Pin K10):
Serial Interface Chip Select Input. In serial internally pulled low with 200kΩ to GND. If EIP2 = high programming mode (PAR/SER = GND), CS is the serial (the input voltage is higher than 2.0V), the IP2 adjust interface chip select input. When CS is low, SCK is enabled circuit is enabled. If EIP2 = low (the input voltage is less for shifting data on SDI into the mode control registers. than 1.0V), it is disabled. In the parallel programming mode (PAR/SER = VDD), CS controls the clock duty stabilizer (see Table 4). CS can be
NC1, NC2, NC3 (Pins C6, C9, D9):
Do Not Connect. driven with 1.8V to 3.3V logic.
EN_I (Pin C14):
First Amplifier I Channel Enable Pin. Pin
PAR/SER (Pin J10):
Programming Mode Selection Pin. is internally pulled high with 100kΩ to VCC2. Assert pin to Connect to GND to enable the serial programming mode a low voltage to enable the amplifier. Connect pin to GND where CS, SCK, SDI, SDO become a serial interface that if enable function is not used. controls the ADC operating modes. Connect to VDD to enable
EN_Q (Pin C3):
First Amplifier Q Channel Enable Pin. Pin the parallel programming mode where CS, SCK, SDI, SDO is internally pulled high with 100kΩ to VCC2. Assert pin to become parallel logic inputs that control a reduced set of a low voltage to enable the amplifier. Connect pin to GND the ADC operating modes. PAR/SER should be connected if enable function is not used. directly to GND or VDD and not be driven by a logic signal.
SHDN_I (Pin D14):
Amplifier I Channel Shutdown Pin.
Digital Outputs
Pin is internally pulled high with 100kΩ to VCC2. Assert pin to a low voltage to shut down the amplifier. Proper
SDO (Pin L11):
Serial Interface Data Output. In serial pro- sequencing of the EN_I and SHDN_I pins is required to gramming mode (PAR/SER = GND), SDO is the optional avoid non-monotonic output signal behavior. Connect pin serial inter-face data output. Data on SDO is read back from to V the mode control registers and can be latched on the falling CC2 if shutdown function is not used. edge of SCK. SDO is an open-drain N-channel MOSFET
SHDN_Q (Pin D3):
Amplifier Q Channel Shutdown Pin. output that requires an external 2kΩ pull-up resistor from Pin is internally pulled high with 100kΩ to VCC2. Assert 1.8V to 3.3V. If readback from the mode control registers pin to a low voltage to shut down the amplifier. Proper is not needed, the pull-up resistor is not necessary and sequencing of the EN_Q and SHDN_Q pins is required to SDO can be left unconnected. avoid non-monotonic output signal behavior. Connect pin to VCC2 if shutdown function is not used.
LVDS Digital Outputs SDI (Pin K11):
Serial Interface Data Input. In serial pro- The following pins are differential LVDS outputs. The output gramming mode, (PAR/SER = GND), SDI is the serial current level is programmable. There is an optional internal interface data input. Data on SDI is clocked into the mode 100Ω termination resistor between the pins of each LVDS control registers on the rising edge of SCK. In the parallel output pair. programming mode (PAR/SER = VDD), SDI selects 3.5mA or a 7.5mA LVDS output current (see Table 4). SDI can be driven with 1.8V to 3.3V logic. 9013fa 10 For more information www.linear.com/LTM9013 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Dynamic Accuracy Analog Inputs and Outputs Digital Inputs and Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagrams Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
pin FuncTions Control Pins SCK (Pin J11):
Serial Interface Clock Input. In serial
EN (Pin B8):
Demodulator Enable Pin. If EN = high (the programming mode (PAR/SER = GND), SCK is the serial input voltage is higher than 2.0V), the demodulator is en- interface clock input. In the parallel programming mode abled. If EN = low (the input voltage is less than 1.0V), it (PAR/SER = VDD), SCK can be used to place the part in the is disabled. If the enable function is not needed, then this low power sleep mode (see Table 4). SCK can be driven pin should be tied to V with 1.8V to 3.3V logic. CC1.
EIP2 (Pin D6):
Demodulator IP2 Adjust Enable Pin. Pin is
CS (Pin K10):
Serial Interface Chip Select Input. In serial internally pulled low with 200kΩ to GND. If EIP2 = high programming mode (PAR/SER = GND), CS is the serial (the input voltage is higher than 2.0V), the IP2 adjust interface chip select input. When CS is low, SCK is enabled circuit is enabled. If EIP2 = low (the input voltage is less for shifting data on SDI into the mode control registers. than 1.0V), it is disabled. In the parallel programming mode (PAR/SER = VDD), CS controls the clock duty stabilizer (see Table 4). CS can be
NC1, NC2, NC3 (Pins C6, C9, D9):
Do Not Connect. driven with 1.8V to 3.3V logic.
EN_I (Pin C14):
First Amplifier I Channel Enable Pin. Pin
PAR/SER (Pin J10):
Programming Mode Selection Pin. is internally pulled high with 100kΩ to VCC2. Assert pin to Connect to GND to enable the serial programming mode a low voltage to enable the amplifier. Connect pin to GND where CS, SCK, SDI, SDO become a serial interface that if enable function is not used. controls the ADC operating modes. Connect to VDD to enable
EN_Q (Pin C3):
First Amplifier Q Channel Enable Pin. Pin the parallel programming mode where CS, SCK, SDI, SDO is internally pulled high with 100kΩ to VCC2. Assert pin to become parallel logic inputs that control a reduced set of a low voltage to enable the amplifier. Connect pin to GND the ADC operating modes. PAR/SER should be connected if enable function is not used. directly to GND or VDD and not be driven by a logic signal.
SHDN_I (Pin D14):
Amplifier I Channel Shutdown Pin.
Digital Outputs
Pin is internally pulled high with 100kΩ to VCC2. Assert pin to a low voltage to shut down the amplifier. Proper
SDO (Pin L11):
Serial Interface Data Output. In serial pro- sequencing of the EN_I and SHDN_I pins is required to gramming mode (PAR/SER = GND), SDO is the optional avoid non-monotonic output signal behavior. Connect pin serial inter-face data output. Data on SDO is read back from to V the mode control registers and can be latched on the falling CC2 if shutdown function is not used. edge of SCK. SDO is an open-drain N-channel MOSFET
SHDN_Q (Pin D3):
Amplifier Q Channel Shutdown Pin. output that requires an external 2kΩ pull-up resistor from Pin is internally pulled high with 100kΩ to VCC2. Assert 1.8V to 3.3V. If readback from the mode control registers pin to a low voltage to shut down the amplifier. Proper is not needed, the pull-up resistor is not necessary and sequencing of the EN_Q and SHDN_Q pins is required to SDO can be left unconnected. avoid non-monotonic output signal behavior. Connect pin to VCC2 if shutdown function is not used.
LVDS Digital Outputs SDI (Pin K11):
Serial Interface Data Input. In serial pro- The following pins are differential LVDS outputs. The output gramming mode, (PAR/SER = GND), SDI is the serial current level is programmable. There is an optional internal interface data input. Data on SDI is clocked into the mode 100Ω termination resistor between the pins of each LVDS control registers on the rising edge of SCK. In the parallel output pair. programming mode (PAR/SER = VDD), SDI selects 3.5mA or a 7.5mA LVDS output current (see Table 4). SDI can be driven with 1.8V to 3.3V logic. 9013fa 10 For more information www.linear.com/LTM9013 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Dynamic Accuracy Analog Inputs and Outputs Digital Inputs and Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagrams Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
