Datasheet LTC1391 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | 8-Channel Analog Multiplexer with Cascadable Serial Interface |
| Pages / Page | 12 / 6 — APPLICATIONS INFORMATION. Multiplexer Operation. Table 1. Logic Table for … |
| Revision | LTC1391: 8-Channel Analog Multiplexer with Cascadable Serial Interface Data Sheet |
| File Format / Size | PDF / 185 Kb |
| Document Language | English |
APPLICATIONS INFORMATION. Multiplexer Operation. Table 1. Logic Table for Channel Selection. ACTIVE CHANNEL
Model Line for this Datasheet
Text Version of Document
LTC1391
U U W U APPLICATIONS INFORMATION Multiplexer Operation
selection of next channel. If the “EN” bit is logic low, as illustrated in the second data sequence, it disables all Figure 1 shows the block diagram of the components channels and there will be no analog signal transmission. within the LTC1391 required for MUX operation. The Table 1 shows the various bit combinations for channel LTC1391 uses DIN to select the active channel and the chip selection. select input, CS, to switch on the selected channel as shown in Figure 2.
Table 1. Logic Table for Channel Selection
When CS is high, the input data on the D
ACTIVE CHANNEL EN B2 B1 BO
IN pin is latched into the 4-bit shift register on the rising clock edge. The All Off 0 X X X input data consists of the “EN” bit and a string of three bits S0 1 0 0 0 for channel selection. If “EN” bit is logic high as illustrated S1 1 0 0 1 in the first input data sequence, it enables the selected S2 1 0 1 0 channel. After the clocking in of the last channel selection S3 1 0 1 1 bit B0, the CS pin must be pulled low before the next rising S4 1 1 0 0 clock edge to ensure correct operation. Once CS is pulled S5 1 1 0 1 low, the previously selected channel is switched off to S6 1 1 1 0 ensure a break-before-make interval. After a delay of t S7 1 1 1 1 ON, the selected channel is switched on allowing signal trans- mission. The selected channel remains on until the next
Digital Data Transfer Operation
falling edge of CS. After a delay of tOFF, the LTC1391 The block diagram of Figure 3 shows the components terminates the analog signal transmission and allows the within the LTC1391 required for serial data transfer. When CS is held high, data is fed into the 4-bit shift register and CLK then shifted to D CONTROL 4-BIT SHIFT OUT. Data appears at DOUT after the fourth DIN LOGIC REGISTER rising edge of the clock as shown in Figure 4. The last four CS CLK CONTROL 4-BIT SHIFT D DOUT ANALOG INPUTS MUX ANALOG IN LOGIC REGISTER (S0 TO S7) BLOCK OUTPUT (D) CS 1391 F03 1391 • F01
Figure 3. Simplified Block Diagram of the Figure 1. Simplified Block Diagram of the MUX Operation Digital Data Transfer Operation
CLK CS EN D B2 B1 B0 EN LO B2 B1 B0 IN HIGH ANY ANALOG INPUT D tON tOFF 1391 • F02
Figure 2. Multiplexer Operation
sn1391 1391fas 6
U U W U APPLICATIONS INFORMATION Multiplexer Operation
selection of next channel. If the “EN” bit is logic low, as illustrated in the second data sequence, it disables all Figure 1 shows the block diagram of the components channels and there will be no analog signal transmission. within the LTC1391 required for MUX operation. The Table 1 shows the various bit combinations for channel LTC1391 uses DIN to select the active channel and the chip selection. select input, CS, to switch on the selected channel as shown in Figure 2.
Table 1. Logic Table for Channel Selection
When CS is high, the input data on the D
ACTIVE CHANNEL EN B2 B1 BO
IN pin is latched into the 4-bit shift register on the rising clock edge. The All Off 0 X X X input data consists of the “EN” bit and a string of three bits S0 1 0 0 0 for channel selection. If “EN” bit is logic high as illustrated S1 1 0 0 1 in the first input data sequence, it enables the selected S2 1 0 1 0 channel. After the clocking in of the last channel selection S3 1 0 1 1 bit B0, the CS pin must be pulled low before the next rising S4 1 1 0 0 clock edge to ensure correct operation. Once CS is pulled S5 1 1 0 1 low, the previously selected channel is switched off to S6 1 1 1 0 ensure a break-before-make interval. After a delay of t S7 1 1 1 1 ON, the selected channel is switched on allowing signal trans- mission. The selected channel remains on until the next
Digital Data Transfer Operation
falling edge of CS. After a delay of tOFF, the LTC1391 The block diagram of Figure 3 shows the components terminates the analog signal transmission and allows the within the LTC1391 required for serial data transfer. When CS is held high, data is fed into the 4-bit shift register and CLK then shifted to D CONTROL 4-BIT SHIFT OUT. Data appears at DOUT after the fourth DIN LOGIC REGISTER rising edge of the clock as shown in Figure 4. The last four CS CLK CONTROL 4-BIT SHIFT D DOUT ANALOG INPUTS MUX ANALOG IN LOGIC REGISTER (S0 TO S7) BLOCK OUTPUT (D) CS 1391 F03 1391 • F01
Figure 3. Simplified Block Diagram of the Figure 1. Simplified Block Diagram of the MUX Operation Digital Data Transfer Operation
CLK CS EN D B2 B1 B0 EN LO B2 B1 B0 IN HIGH ANY ANALOG INPUT D tON tOFF 1391 • F02
Figure 2. Multiplexer Operation
sn1391 1391fas 6
