Datasheet LT1529, LT1529-3.3, LT1529-5 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | 3A Low Dropout Regulators with Micropower Quiescent Current and Shutdown |
| Pages / Page | 12 / 7 — TYPICAL PERFOR A CE CH. ARA TERISTICS. Load Regulation. LT1529-5 … |
| File Format / Size | PDF / 154 Kb |
| Document Language | English |
TYPICAL PERFOR A CE CH. ARA TERISTICS. Load Regulation. LT1529-5 Transient Response. PI FU CTIO S. OUTPUT (Pin 1):
Model Line for this Datasheet
- LT1529CQ#PBF LT1529CQ#PBF LT1529CQ#TRPBF LT1529CQ#TRPBF LT1529CQ-3.3#PBF LT1529CQ-3.3#PBF LT1529CQ-3.3#TRPBF LT1529CQ-3.3#TRPBF LT1529CQ-5#PBF LT1529CQ-5#PBF LT1529CQ-5#TRPBF LT1529CQ-5#TRPBF LT1529CT#06PBF LT1529CT#06PBF LT1529CT#PBF LT1529CT#PBF LT1529CT-3.3#06PBF LT1529CT-3.3#06PBF LT1529CT-3.3#PBF LT1529CT-3.3#PBF LT1529CT-5#06PBF LT1529CT-5#06PBF LT1529CT-5#30PBF LT1529CT-5#30PBF LT1529CT-5#PBF LT1529CT-5#PBF LT1529IQ#PBF LT1529IQ#PBF LT1529IQ#TRPBF LT1529IQ#TRPBF LT1529IQ-3.3#PBF LT1529IQ-3.3#PBF LT1529IQ-3.3#TRPBF LT1529IQ-3.3#TRPBF LT1529IQ-5#PBF LT1529IQ-5#PBF LT1529IQ-5#TRPBF LT1529IQ-5#TRPBF LT1529IT#06PBF LT1529IT#06PBF LT1529IT#PBF LT1529IT#PBF LT1529IT-3.3#PBF LT1529IT-3.3#PBF LT1529IT-5#PBF LT1529IT-5#PBF
Text Version of Document
LT1529 LT1529-3.3/LT1529-5
W U TYPICAL PERFOR A CE CH C ARA TERISTICS Load Regulation LT1529-5 Transient Response LT1529-5 Transient Response
5 V V LT1529-5 IN = 6V IN = 6V 0.2 0.2 C C IN = 3.3µF IN = 10µF 0 C C 0.1 OUT = 47µF 0.1 OUT = 22µF 0 0 –5 LT1529-3.3 LT1529 – 0.1 – 0.1 DEVIATION (V) DEVIATION (V) –10 OUTPUT VOLTAGE OUTPUT VOLTAGE – 0.2 – 0.2 –15 3 3 LOAD REGULATION (mV) 2 2 –20 VIN = VOUT (NOMINAL) + 1V ∆ILOAD = 100mA to 3A 1 1 VADJ = VOUT –25 LOAD CURRENT (A) LOAD CURRENT (A) – 50 – 25 0 25 50 75 100 125 0 100 200 300 400 500 600 700 800 900 1000 0 20 40 60 80 100 120 140 160 180 200 TEMPERATURE (°C) TIME (µs) TIME (µs) LT1529 • G28 LT1529 • G29 LT1529 • G30
U U U PI FU CTIO S OUTPUT (Pin 1):
OUTPUT Pin. The OUTPUT pin supplies R 5 1 P VIN OUTPUT power to the load. A minimum output capacitor of 22µF is LT1529-5 required to prevent oscillations. Larger values will be 4 2 SHDN SENSE + LOAD + required to optimize transient response for large load VIN GND current deltas. See the Applications Information section 3 for further information on output capacitance and reverse RP LT1529 • F01 output characteristics.
Figure 1. Kelvin Sense Connection SENSE (Pin 2):
SENSE Pin. For fixed voltage versions of the LT1529 (LT1529-3.3, LT1529-5) the SENSE pin is the pin is internally clamped to 6V and – 0.6V (one VBE). This input to the error amplifier. Optimum regulation will be pin has a bias current of 150nA which flows into the pin. obtained at the point where the SENSE pin is connected to See Bias Current curve in the Typical Performance Char- the output pin. For most applications the SENSE pin is acteristics. The ADJ pin reference voltage is equal to 3.75V connected directly to the OUTPUT pin at the regulator. In referenced to ground. critical applications small voltage drops caused by the
SHDN (Pin 4):
Shutdown Pin. This pin is used to put the resistance (RP) of PC traces between the regulator and the device into shutdown. In shutdown the output of the load, which would normally degrade regulation, may be device is turned off. This pin is active low. The device will eliminated by connecting the SENSE pin to the OUTPUT be shut down if the SHDN pin is actively pulled low. The pin at the load as shown in Figure 1 (Kelvin Sense Connec- SHDN pin current with the pin pulled to ground will be 6µA. tion). Note that the voltage drop across the external PC The SHDN pin is internally clamped to 7V and – 0.6V (one traces will add to the dropout voltage of the regulator. The V SENSE pin bias current is 15µA at the nominal regulated BE). This allows the SHDN pin to be driven directly by 5V logic or by open-collector logic with a pull-up resistor. The output voltage. This pin is internally clamped to – 0.6V pull-up resistor is only required to supply the leakage (one VBE). current of the open-collector gate, normally several mi-
ADJ (Pin 2):
Adjust Pin. For the LT1529 (adjustable croamperes. Pull-up current must be limited to a maxi- version) the ADJ pin is the input to the error amplifier. This mum of 5mA. A curve of SHDN pin input current as a 152935fb 7
W U TYPICAL PERFOR A CE CH C ARA TERISTICS Load Regulation LT1529-5 Transient Response LT1529-5 Transient Response
5 V V LT1529-5 IN = 6V IN = 6V 0.2 0.2 C C IN = 3.3µF IN = 10µF 0 C C 0.1 OUT = 47µF 0.1 OUT = 22µF 0 0 –5 LT1529-3.3 LT1529 – 0.1 – 0.1 DEVIATION (V) DEVIATION (V) –10 OUTPUT VOLTAGE OUTPUT VOLTAGE – 0.2 – 0.2 –15 3 3 LOAD REGULATION (mV) 2 2 –20 VIN = VOUT (NOMINAL) + 1V ∆ILOAD = 100mA to 3A 1 1 VADJ = VOUT –25 LOAD CURRENT (A) LOAD CURRENT (A) – 50 – 25 0 25 50 75 100 125 0 100 200 300 400 500 600 700 800 900 1000 0 20 40 60 80 100 120 140 160 180 200 TEMPERATURE (°C) TIME (µs) TIME (µs) LT1529 • G28 LT1529 • G29 LT1529 • G30
U U U PI FU CTIO S OUTPUT (Pin 1):
OUTPUT Pin. The OUTPUT pin supplies R 5 1 P VIN OUTPUT power to the load. A minimum output capacitor of 22µF is LT1529-5 required to prevent oscillations. Larger values will be 4 2 SHDN SENSE + LOAD + required to optimize transient response for large load VIN GND current deltas. See the Applications Information section 3 for further information on output capacitance and reverse RP LT1529 • F01 output characteristics.
Figure 1. Kelvin Sense Connection SENSE (Pin 2):
SENSE Pin. For fixed voltage versions of the LT1529 (LT1529-3.3, LT1529-5) the SENSE pin is the pin is internally clamped to 6V and – 0.6V (one VBE). This input to the error amplifier. Optimum regulation will be pin has a bias current of 150nA which flows into the pin. obtained at the point where the SENSE pin is connected to See Bias Current curve in the Typical Performance Char- the output pin. For most applications the SENSE pin is acteristics. The ADJ pin reference voltage is equal to 3.75V connected directly to the OUTPUT pin at the regulator. In referenced to ground. critical applications small voltage drops caused by the
SHDN (Pin 4):
Shutdown Pin. This pin is used to put the resistance (RP) of PC traces between the regulator and the device into shutdown. In shutdown the output of the load, which would normally degrade regulation, may be device is turned off. This pin is active low. The device will eliminated by connecting the SENSE pin to the OUTPUT be shut down if the SHDN pin is actively pulled low. The pin at the load as shown in Figure 1 (Kelvin Sense Connec- SHDN pin current with the pin pulled to ground will be 6µA. tion). Note that the voltage drop across the external PC The SHDN pin is internally clamped to 7V and – 0.6V (one traces will add to the dropout voltage of the regulator. The V SENSE pin bias current is 15µA at the nominal regulated BE). This allows the SHDN pin to be driven directly by 5V logic or by open-collector logic with a pull-up resistor. The output voltage. This pin is internally clamped to – 0.6V pull-up resistor is only required to supply the leakage (one VBE). current of the open-collector gate, normally several mi-
ADJ (Pin 2):
Adjust Pin. For the LT1529 (adjustable croamperes. Pull-up current must be limited to a maxi- version) the ADJ pin is the input to the error amplifier. This mum of 5mA. A curve of SHDN pin input current as a 152935fb 7
