Datasheet LT1534 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Ultralow Noise 2A Switching Regulators |
| Pages / Page | 16 / 10 — APPLICATIONS INFORMATION. Thermal Considerations. Negative Output Voltage … |
| File Format / Size | PDF / 216 Kb |
| Document Language | English |
APPLICATIONS INFORMATION. Thermal Considerations. Negative Output Voltage Setting. Figure 3
Model Line for this Datasheet
Text Version of Document
LT1534/LT1534-1
U U W U APPLICATIONS INFORMATION
One word of caution. Sometimes a feedback zero is added
Thermal Considerations
to the control loop by placing a capacitor across R1 above. Computing power dissipation for this IC requires careful If the feedback zero capacitively pulls the FB pin above the attention to detail. Reduced output slewing causes the part internal regulator voltage (2.4V typ), output regulation to dissipate more power than would occur with fast edges. may be disrupted. A series resistance with the feedback However, much improvement in noise can be produced pin can eliminate this potential problem. with modest decrease in supply efficiency.
Negative Output Voltage Setting
Power dissipation is a function of topology, input voltage, switch current and slew rates. It is impractical to come up Negative output voltage can be sensed using the NFB pin. with an all-encompassing formula. It is therefore recom- In this case regulation will occur when the NFB pin is at mended that package temperature be measured in each – 2.5V. The input bias current for the NFB pin is –25µA application. The part has an internal thermal shutdown to (INFB) and must be accounted for when selecting divider prevent device destruction, but this should not replace resistor values. careful thermal design. R1 NFB PIN –VOUT 1. Dissipation due to input current: INFB R2 I 1534 F02 P = V m 11 A VIN IN + 60
Figure 3
where I is the average switch current. Referring to Figure 3, R1 is chosen such that: 2. Dissipation due to the driver saturation: PVSAT = (VSAT)(I)(DCMAX) VOUT − 2 5 . R1= R2 • where VSAT is the output saturation voltage which is 2 5 . + R2 • 25 A µ approximately 0.1 + (0.2)(I), DCMAX is the maximum duty cycle. A suggested value for R2 is 2.5k. The NFB pin is normally left open if the FB pin is being used. 3. Dissipation due to output slew using approximations for slew rates:
Dual Polarity Output Voltage Sensing
Certain applications may benefit from sensing both posi- 2 2 2 2 I V ∆ SAT V I I V tive and negative output voltages. When doing this each ( ) () − IN + IN 4 4 output voltage resistor divider is individually set as previ- P = R + R f 9 9 ( ) ( ) ( ) SLEW CSL VSL OSC ously described. When both FB and NFB pins are used, the ( ) 33 10 ( ) 220 10 LT1534 will act to prevent either output from going beyond its set output voltage. The highest output (lightest load) will dominate control of the regulator. This technique Note if VSAT and ∆I are small with respect to VIN and I, would prevent either output from going unregulated high then: at no load. However, this technique will also compromise output load regulation. I R V R ()( ) ( )( ) CSL IN VSL P = + f V I 9 9 ( )( )() SLEW OSC IN
Shutdown
( ) 33 10 ( ) 220 10 If the shutdown pin is pulled low, the regulator will turn off. The supply current will be reduced to less than 20µA. 10
U U W U APPLICATIONS INFORMATION
One word of caution. Sometimes a feedback zero is added
Thermal Considerations
to the control loop by placing a capacitor across R1 above. Computing power dissipation for this IC requires careful If the feedback zero capacitively pulls the FB pin above the attention to detail. Reduced output slewing causes the part internal regulator voltage (2.4V typ), output regulation to dissipate more power than would occur with fast edges. may be disrupted. A series resistance with the feedback However, much improvement in noise can be produced pin can eliminate this potential problem. with modest decrease in supply efficiency.
Negative Output Voltage Setting
Power dissipation is a function of topology, input voltage, switch current and slew rates. It is impractical to come up Negative output voltage can be sensed using the NFB pin. with an all-encompassing formula. It is therefore recom- In this case regulation will occur when the NFB pin is at mended that package temperature be measured in each – 2.5V. The input bias current for the NFB pin is –25µA application. The part has an internal thermal shutdown to (INFB) and must be accounted for when selecting divider prevent device destruction, but this should not replace resistor values. careful thermal design. R1 NFB PIN –VOUT 1. Dissipation due to input current: INFB R2 I 1534 F02 P = V m 11 A VIN IN + 60
Figure 3
where I is the average switch current. Referring to Figure 3, R1 is chosen such that: 2. Dissipation due to the driver saturation: PVSAT = (VSAT)(I)(DCMAX) VOUT − 2 5 . R1= R2 • where VSAT is the output saturation voltage which is 2 5 . + R2 • 25 A µ approximately 0.1 + (0.2)(I), DCMAX is the maximum duty cycle. A suggested value for R2 is 2.5k. The NFB pin is normally left open if the FB pin is being used. 3. Dissipation due to output slew using approximations for slew rates:
Dual Polarity Output Voltage Sensing
Certain applications may benefit from sensing both posi- 2 2 2 2 I V ∆ SAT V I I V tive and negative output voltages. When doing this each ( ) () − IN + IN 4 4 output voltage resistor divider is individually set as previ- P = R + R f 9 9 ( ) ( ) ( ) SLEW CSL VSL OSC ously described. When both FB and NFB pins are used, the ( ) 33 10 ( ) 220 10 LT1534 will act to prevent either output from going beyond its set output voltage. The highest output (lightest load) will dominate control of the regulator. This technique Note if VSAT and ∆I are small with respect to VIN and I, would prevent either output from going unregulated high then: at no load. However, this technique will also compromise output load regulation. I R V R ()( ) ( )( ) CSL IN VSL P = + f V I 9 9 ( )( )() SLEW OSC IN
Shutdown
( ) 33 10 ( ) 220 10 If the shutdown pin is pulled low, the regulator will turn off. The supply current will be reduced to less than 20µA. 10
