Datasheet LTC3828 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Dual, 2-Phase Step-Down Controller with Tracking |
| Pages / Page | 32 / 10 — OPERATION (Refer to Functional Diagram) Main Control Loop. Table 1. … |
| File Format / Size | PDF / 388 Kb |
| Document Language | English |
OPERATION (Refer to Functional Diagram) Main Control Loop. Table 1. FCB/PLLIN PIN. CONDITION. Low Current Operation
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LTC3828
OPERATION (Refer to Functional Diagram) Main Control Loop
enters Burst Mode operation. Burst Mode operation sets The IC uses a constant frequency, current mode step-down a minimum output current level before inhibiting the top architecture with the two controller channels operating switch and turns off the synchronous MOSFET(s) when 180 degrees out of phase. During normal operation, each the inductor current goes negative. This combination of top MOSFET is turned on when the clock for that channel requirements will, at low currents, force the ITH pin below sets the RS latch, and turned off when the main current a voltage threshold that will temporarily inhibit turn-on of comparator, I both output MOSFETs until the output voltage drops. There 1, resets the RS latch. The peak inductor current at which I is 60mV of hysteresis in the burst comparator B tied to 1 resets the RS latch is controlled by the voltage on the I the ITH pin. This hysteresis produces output signals to the TH pin, which is the output of each error amplifi er EA. The V MOSFETs that turn them on for several cycles, followed by OSENSE pin receives the voltage feedback signal, which is compared to the internal refer- a variable “sleep” interval depending upon the load current. ence voltage by the EA. When the load current increases, The resultant output voltage ripple is held to a very small it causes a slight decrease in V value by having the hysteretic comparator after the error OSENSE relative to the 0.8V reference, which in turn causes the I amplifi er gain block. When the FCB/PLLIN pin voltage is TH voltage to increase until the average inductor current matches the new load above 4.8V, the controller operates in constant frequency current. After the top MOSFET has turned off, the bottom mode and the synchronous MOSFET is turned off when MOSFET is turned on until either the inductor current inductor current nears zero in each cycle. starts to reverse, as indicated by current comparator I2, In order to prevent erratic operation if no external con- or the beginning of the next cycle. nections are made to the FCB/PLLIN pin, the FCB/PLLIN The top MOSFET drivers are biased from fl oating bootstrap pin has a 0.18μA internal current source pulling the pin capacitor, C high. B, which normally is recharged during each off cycle through an external diode when the top MOSFET The following table summarizes the possible states avail- turns off. As VIN decreases to a voltage close to VOUT , able on the FCB/PLLIN pin: the loop may enter dropout and attempt to turn on the top MOSFET continuously. The dropout detector detects
Table 1
this and forces the top MOSFET off for about 400ns every
FCB/PLLIN PIN CONDITION
tenth cycle to allow C 0V to 0.75V Forced Continuous Both Controllers B to recharge. (Current Reversal Allowed— The main control loop is shut down by pulling the RUN Burst Inhibited) pin low. When the RUN pin reaches 1.5V, the main control 0.85V < VFCB/PLLIN < 4.3V Minimum Peak Current Induces or Open Burst Mode Operation loop is enabled. When both RUN1 and RUN2 are low, No Current Reversal Allowed all controller functions are shut down, including the 5V >4.8V Burst Mode Operation Disabled regulator. Constant Frequency Mode Enabled No Current Reversal Allowed No Minimum Peak Current
Low Current Operation
The FCB/PLLIN pin is a multifunction pin providing two Besides providing a logic input to select light load op- functions: 1) to accept external clock signal; and 2) to eration mode, the FCB/PLLIN pin acts as the input for select among three modes of light load operations. When external clock synchronization. Upon detecting the pres- the FCB/PLLIN pin voltage is below 0.75V, the control- ence of an external clock signal, channel 1 will lock on to ler forces continuous PWM current mode operation. In this external clock and this will be followed by channel 2 this mode, the top and bottom MOSFETs are alternately (see Frequency Synchronization section). The LTC3828 turned on to maintain the output voltage independent of defaults to forced continuous mode when sychronized to direction of inductor current. When the FCB/PLLIN pin is an external clock. below VINTVCC – 0.7V but greater than 0.8V, the controller 3828fc 10
OPERATION (Refer to Functional Diagram) Main Control Loop
enters Burst Mode operation. Burst Mode operation sets The IC uses a constant frequency, current mode step-down a minimum output current level before inhibiting the top architecture with the two controller channels operating switch and turns off the synchronous MOSFET(s) when 180 degrees out of phase. During normal operation, each the inductor current goes negative. This combination of top MOSFET is turned on when the clock for that channel requirements will, at low currents, force the ITH pin below sets the RS latch, and turned off when the main current a voltage threshold that will temporarily inhibit turn-on of comparator, I both output MOSFETs until the output voltage drops. There 1, resets the RS latch. The peak inductor current at which I is 60mV of hysteresis in the burst comparator B tied to 1 resets the RS latch is controlled by the voltage on the I the ITH pin. This hysteresis produces output signals to the TH pin, which is the output of each error amplifi er EA. The V MOSFETs that turn them on for several cycles, followed by OSENSE pin receives the voltage feedback signal, which is compared to the internal refer- a variable “sleep” interval depending upon the load current. ence voltage by the EA. When the load current increases, The resultant output voltage ripple is held to a very small it causes a slight decrease in V value by having the hysteretic comparator after the error OSENSE relative to the 0.8V reference, which in turn causes the I amplifi er gain block. When the FCB/PLLIN pin voltage is TH voltage to increase until the average inductor current matches the new load above 4.8V, the controller operates in constant frequency current. After the top MOSFET has turned off, the bottom mode and the synchronous MOSFET is turned off when MOSFET is turned on until either the inductor current inductor current nears zero in each cycle. starts to reverse, as indicated by current comparator I2, In order to prevent erratic operation if no external con- or the beginning of the next cycle. nections are made to the FCB/PLLIN pin, the FCB/PLLIN The top MOSFET drivers are biased from fl oating bootstrap pin has a 0.18μA internal current source pulling the pin capacitor, C high. B, which normally is recharged during each off cycle through an external diode when the top MOSFET The following table summarizes the possible states avail- turns off. As VIN decreases to a voltage close to VOUT , able on the FCB/PLLIN pin: the loop may enter dropout and attempt to turn on the top MOSFET continuously. The dropout detector detects
Table 1
this and forces the top MOSFET off for about 400ns every
FCB/PLLIN PIN CONDITION
tenth cycle to allow C 0V to 0.75V Forced Continuous Both Controllers B to recharge. (Current Reversal Allowed— The main control loop is shut down by pulling the RUN Burst Inhibited) pin low. When the RUN pin reaches 1.5V, the main control 0.85V < VFCB/PLLIN < 4.3V Minimum Peak Current Induces or Open Burst Mode Operation loop is enabled. When both RUN1 and RUN2 are low, No Current Reversal Allowed all controller functions are shut down, including the 5V >4.8V Burst Mode Operation Disabled regulator. Constant Frequency Mode Enabled No Current Reversal Allowed No Minimum Peak Current
Low Current Operation
The FCB/PLLIN pin is a multifunction pin providing two Besides providing a logic input to select light load op- functions: 1) to accept external clock signal; and 2) to eration mode, the FCB/PLLIN pin acts as the input for select among three modes of light load operations. When external clock synchronization. Upon detecting the pres- the FCB/PLLIN pin voltage is below 0.75V, the control- ence of an external clock signal, channel 1 will lock on to ler forces continuous PWM current mode operation. In this external clock and this will be followed by channel 2 this mode, the top and bottom MOSFETs are alternately (see Frequency Synchronization section). The LTC3828 turned on to maintain the output voltage independent of defaults to forced continuous mode when sychronized to direction of inductor current. When the FCB/PLLIN pin is an external clock. below VINTVCC – 0.7V but greater than 0.8V, the controller 3828fc 10
