Datasheet AD9684 (Analog Devices) - 9

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AD9684 Data Sheet Parameter Temperature Min Typ Max Unit
APERTURE Aperture Delay (tA) Full 530 ps Aperture Uncertainty (Jitter, tj) Full 55 fs rms Out of Range Recovery Time Full 1 Clock Cycles 1 The maximum sample rate is the clock rate after the divider. 2 The minimum sample rate operates at 300 MSPS. 3 This specification is valid for parallel interleaved, channel multiplexed, and byte mode output modes. 4 This specification is valid for byte mode output mode only. 5 No DDCs used. 6 Wake-up time is defined as the time required to return to normal operation from power-down mode or standby mode.
TIMING SPECIFICATIONS Table 5. Parameter Description Min Typ Max Unit
CLK± to SYNC± TIMING REQUIREMENTS See Figure 2 tSU_SR Device clock to SYNC± setup time 117 ps tH_SR Device clock to SYNC± hold time −96 ps SPI TIMING REQUIREMENTS See Figure 3 tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns tCLK Period of the SCLK 40 ns tS Setup time between CSB and SCLK 2 ns tH Hold time between CSB and SCLK 2 ns tHIGH Minimum period that SCLK must be in a logic high state 10 ns tLOW Minimum period that SCLK must be in a logic low state 10 ns tEN_SDIO Time required for the SDIO pin to switch from an input to an 10 ns output relative to the SCLK falling edge (not shown in Figure 3) tDIS_SDIO Time required for the SDIO pin to switch from an output to an 10 ns input relative to the SCLK rising edge (not shown in Figure 3)
Timing Diagrams CLK– CLK+ tSU_SR tH_SR SYNC–
002
SYNC+
13015- Figure 2. SYNC± Setup and Hold Timing
t t t DS HIGH CLK tH tS tDH tLOW CSB SCLK DON’T CARE DON’T CARE
003
SDIO DON’T CARE R/W A14 A13 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE
13015- Figure 3. Serial Port Interface Timing Diagram Rev. 0 | Page 8 of 64 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Controls and SFDR Optimization Absolute Maximum Input Swing VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjustment Clock Fine Delay Adjustment Clock Jitter Considerations POWER-DOWN/STANDBY MODE TEMPERATURE DIODE ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A AND FD_B) SIGNAL MONITOR DIGITAL DOWNCONVERTERS (DDCs) DDC I/Q INPUT SELECTION DDC I/Q OUTPUT SELECTION DDC GENERAL DESCRIPTION FREQUENCY TRANSLATION GENERAL DESCRIPTION Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO PLUS MIXER LOSS AND SFDR NUMERICALLY CONTROLLED OSCILLATOR Setting Up the NCO FTW and POW NCO Synchronization Mixer FIR FILTERS GENERAL DESCRIPTION HALF-BAND FILTERS HB4 Filter HB3 Filter HB2 Filter HB1 Filter DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION BLOCK DDC EXAMPLE CONFIGURATIONS DIGITAL OUTPUTS DIGITAL OUTPUTS Timing Data Clock Output ADC OVERRANGE MULTICHIP SYNCHRONIZATION SYNC± SETUP AND HOLD WINDOW MONITOR TEST MODES ADC TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Unassigned and Reserved Locations Default Values Logic Levels Channel-Specific Registers SPI Soft Reset MEMORY MAP REGISTER TABLE APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS OUTLINE DIMENSIONS ORDERING GUIDE