Datasheet AD7177-2 (Analog Devices) - 48

Data Sheet AD7177-2 GROUNDING AND LAYOUT
The analog inputs and reference inputs are differential and, possible to provide low impedance paths and reduce glitches on therefore, most of the voltages in the analog modulator are the power supply line. Shield fast switching signals like clocks common-mode voltages. The high common-mode rejection of with digital ground to prevent radiating noise to other sections the device removes common-mode noise on these inputs. The of the board and never run clock signals near the analog inputs. analog and digital supplies to the AD7177-2 are independent Avoid crossover of digital and analog signals. Run traces on and connected to separate pins to minimize coupling between the opposite sides of the board at right angles to each other. This analog and digital sections of the device. The digital filter technique reduces the effects of feedthrough on the board. A provides rejection of broadband noise on the power supplies, microstrip technique is by far the best method but is not always except at integer multiples of the master clock frequency. possible with a double sided board. The digital filter also removes noise from the analog and Good decoupling is important when using high resolution ADCs. reference inputs, provided that these noise sources do not The AD7177-2 has three power supply pins—AVDD1, AVDD2, saturate the analog modulator. As a result, the AD7177-2 is and IOVDD. The AVDD1 and AVDD2 pins are referenced to more immune to noise interference than a conventional high AVSS, and the IOVDD pin is referenced to DGND. Decouple resolution converter. However, because the resolution of the AVDD1 and AVDD2 with a 10 µF capacitor in paral el with a AD7177-2 is high and the noise levels from the converter are so 0.1 µF capacitor to AVSS on each pin. Place the 0.1 µF capacitor low, take care with regard to grounding and layout. as close as possible to the device on each supply, ideal y right up The PCB that houses the ADC must be designed such that the against the device. Decouple IOVDD with a 10 µF capacitor in analog and digital sections are separated and confined to parallel with a 0.1 µF capacitor to DGND. Decouple all analog certain areas of the board. A minimum etch technique is inputs to AVSS. If an external reference is used, decouple the general y best for ground planes because it results in the best REF+ and REF− pins to AVSS. shielding. The AD7177-2 also has two on-board LDO regulators—one In any layout, the user must consider the flow of currents in the that regulates the AVDD2 supply and one that regulates the system, ensuring that the paths for al return currents are as close as IOVDD supply. For the REGCAPA pin, it is recommended that possible to the paths the currents took to reach their destinations. 1 µF and 0.1 µF capacitors to AVSS be used. Similarly, for the REGCAPD pin, it is recommended that 1 µF and 0.1 µF capaci- Avoid running digital lines under the device because this tors to DGND be used. couples noise onto the die and al ows the analog ground plane to run under the AD7177-2 to prevent noise coupling. The If using the AD7177-2 for split supply operation, a separate power supply lines to the AD7177-2 must use as wide a trace as plane must be used for AVSS. Rev. B | Page 47 of 60 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES DIGITAL COMMUNICATION Accessing the ADC Register Map AD7177-2 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Gain Registers Offset Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION BUFFERED ANALOG INPUT CROSSPOINT MULTIPLEXER Fully Differential Inputs Single-Ended Inputs AD7177-2 REFERENCE External Reference Internal Reference BUFFERED REFERENCE INPUT CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER SINGLE CYCLE SETTLING ENHANCED 50 HZ AND 60 HZ REJECTION FILTERS OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE I/O EXTERNAL MULTIPLEXER CONTROL DELAY 24-BIT/32-BIT CONVERSIONS DOUT_RESET SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR Input/Output DATA_STAT IOSTRENGTH INTERNAL TEMPERATURE SENSOR GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 3 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 3 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 3 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 3 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 3 OUTLINE DIMENSIONS ORDERING GUIDE