Datasheet AD7903 (Analog Devices) - 15

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AD7903 Data Sheet THEORY OF OPERATION INx+ MSB SWITCHES CONTROL LSB SWx+ 32,768C 16,384C 4C 2C C C BUSY REFx COMP CONTROL LOGIC GND OUTPUT CODE 32,768C 16,384C 4C 2C C C LSB SWx– MSB CNVx
011 5-
INx–
175 1 Figure 31. ADC Simplified Schematic
CIRCUIT INFORMATION
the comparator input varies by binary-weighted voltage steps (VREF/2, VREF/4 ... VREF/65,536). The control logic toggles these The AD7903 is a fast, low power, precise, dual 16-bit ADC switches, starting with the MSB, to bring the comparator back using a successive approximation architecture. into a balanced condition. After the completion of this process, The AD7903 is capable of simultaneously converting 1,000,000 the part returns to the acquisition phase, and the control logic samples per second (1 MSPS) and powers down between con- generates the ADC output code and a busy signal indicator. versions. When operating at 10 kSPS, for example, it typically Because the AD7903 has an on-board conversion clock, the consumes 70 μW per ADC, making it ideal for battery-powered serial clock, SCKx, is not required for the conversion process. applications.
Transfer Functions
The AD7903 provides the user with an on-chip track-and-hold and does not exhibit any pipeline delay or latency, making it The ideal transfer characteristic for the AD7903 is shown in ideal for multichannel multiplexed applications. Figure 32 and Table 7. The AD7903 can be interfaced to any 1.8 V to 5 V digital logic
) NT
family. It is available in a 20-lead QSOP that allows flexible
E 011...111 M E
configurations.
011...110 L P 011...101 M
The device is pin-for-pin compatible with the pseudo differential,
CO S
16-bit AD7902.
O W T CONVERTER OPERATION ( E D O
The AD7903 is a dual successive approximation ADC based on a charge redistribution DAC. Figure 31 shows the simplified
ADC C 100...010
schematic of the ADC. The capacitive DAC consists of two
100...001 100...000
identical arrays of 16 binary-weighted capacitors, which are
–FSR –FSR + 1 LSB +FSR – 1 LSB
connected to the two comparator inputs.
–FSR + 0.5 LSB +FSR – 1.5 LSB
12 1
ANALOG INPUT
1755- During the acquisition phase of each ADC, terminals of the 1 Figure 32. ADC Ideal Transfer Function array tied to the input of the comparator are connected to GND via SWx+ and SWx−. All independent switches are connected
Table 7. Output Codes and Ideal Input Voltages
to the analog inputs. Therefore, the capacitor arrays are used as
Analog Input, Digital Output
sampling capacitors and acquire the analog signal on the INx+
Description VREF = 5 V Code (Hex)
and INx− inputs. When the acquisition phase is complete and FSR − 1 LSB +4.999962 V 0x7FFF1 the CNVx input goes high, a conversion phase is initiated. When Midscale + 1 LSB +38.15 μV 0x0001 the conversion phase begins, SWx+ and SWx− are opened first. Midscale 0 V 0x0000 The two capacitor arrays are then disconnected from the inputs Midscale − 1 LSB −38.15 μV 0xFFFF and connected to the GND input. Therefore, the differential −FSR + 1 LSB −4.999962 V 0x8001 voltage between the INx+ and INx− inputs, captured at the end −FSR −5 V 0x80002 of the acquisition phase, is applied to the comparator inputs, 1 This is also the code for an overranged analog input (V causing the comparator to become unbalanced. By switching IN+ − VIN− above VREF − VGND). 2 This is also the code for an underranged analog input (VIN+ − VIN− below VGND). each element of the capacitor array between GND and REFx, Rev. B | Page 14 of 28 Document Outline Features Applications General Description Functional Block Diagram Table of Contents Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Circuit Information Converter Operation Transfer Functions Typical Connection Diagram Analog Inputs Driver Amplifier Choice Single-to-Differential Driver Voltage Reference Input Power Supply Digital Interface CS Mode CS Mode, 3-Wire Interface Without Busy Indicator CS Mode, 3-Wire Interface with Busy Indicator CS Mode, 4-Wire Interface Without Busy Indicator CS Mode, 4-Wire Interface with Busy Indicator Chain Mode Chain Mode Without Busy Indicator Chain Mode with Busy Indicator Applications Information Simultaneous Sampling Functional Safety Considerations Layout Evaluating Performance of the AD7903 Outline Dimensions Ordering Guide