Datasheet AD7175-2 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | 24-Bit, 250 kSPS, Sigma-Delta ADC with 20 µs Settling and True Rail-to-Rail Buffers |
| Pages / Page | 63 / 9 — TIMING DIAGRAMS. CS (I). DOUT/RDY (O). MSB. LSB. SCLK (I). I = INPUT, O = … |
| Revision | B |
| File Format / Size | PDF / 1.1 Mb |
| Document Language | English |
TIMING DIAGRAMS. CS (I). DOUT/RDY (O). MSB. LSB. SCLK (I). I = INPUT, O = OUTPUT. t10. DIN (I)
Model Line for this Datasheet
Text Version of Document
AD7175-2 Data Sheet
TIMING DIAGRAMS CS (I) t t 6 1 t5 DOUT/RDY (O) MSB LSB t t7 2 t3 SCLK (I)
3
t
0
4
-0 8 6 4
I = INPUT, O = OUTPUT
2 1 Figure 2. Read Cycle Timing Diagram
CS (I) t t 8 11 SCLK (I) t9 t10 DIN (I) MSB LSB
4 0 -0 8 6 4
I = INPUT, O = OUTPUT
2 1 Figure 3. Write Cycle Timing Diagram Rev. B | Page 8 of 62
TIMING DIAGRAMS CS (I) t t 6 1 t5 DOUT/RDY (O) MSB LSB t t7 2 t3 SCLK (I)
3
t
0
4
-0 8 6 4
I = INPUT, O = OUTPUT
2 1 Figure 2. Read Cycle Timing Diagram
CS (I) t t 8 11 SCLK (I) t9 t10 DIN (I) MSB LSB
4 0 -0 8 6 4
I = INPUT, O = OUTPUT
2 1 Figure 3. Write Cycle Timing Diagram Rev. B | Page 8 of 62
