Datasheet AD7175-8 (Analog Devices) - 41

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AD7175-8 Data Sheet DIGITAL INTERFACE
The programmable functions of the AD7175-8 are control ed via For CRC checksum calculations during a write operation, the the SPI serial interface. The serial interface of the AD7175-8 following polynomial is always used: consists of four signals: CS, DIN, SCLK, and DOUT/RDY. The x8 + x2 + x + 1 DIN input is used to transfer data into the on-chip registers, and the DOUT output is used to access data from the on-chip During read operations, the user can select between this registers. SCLK is the serial clock input for the device, and all data polynomial and a simpler exclusive OR (XOR) function. The transfers (either on the DIN input or on the DOUT output) occur XOR function requires less time to process on the host with respect to the SCLK signal. microcontroller than the polynomial-based checksum. The CRC_EN bits in the interface mode register enable and disable The DOUT/RDY pin also functions as a data ready signal, with the checksum and al ow the user to select between the the output going low if CS is low when a new data-word is polynomial check and the simple XOR check. available in the data register. The RDY output is reset high when The checksum is appended to the end of each read and write a read operation from the data register is complete. The RDY transaction. The checksum calculation for the write transaction output also goes high before updating the data register to is calculated using the 8-bit command word and the 8-bit to indicate when not to read from the device to ensure that a data 24-bit data. For a read transaction, the checksum is calculated read is not attempted while the register is being updated. Take using the command word and the 8-bit to 32-bit data output. care to avoid reading from the data register when the RDY Figure 70 and Figure 71 show SPI write and read transactions, output is about to go low. The best method to ensure that no data respectively. read occurs is to always monitor the RDY output; start reading
8-BIT COMMAND UP TO 24-BIT INPUT 8-BIT CRC
the data register as soon as the RDY output goes low; and
CS
ensure a sufficient SCLK rate, such that the read is complete before the next conversion result. CS is used to select a device. It can be used to decode the AD7175-8 in systems where several
CS DATA CRC DIN
components are connected to the serial bus. Figure 2 and Figure 3 show timing diagrams for interfacing to
SCLK
074 1- 1 the AD7175-8 using CS to decode the device. Figure 2 shows 129 the timing for a read operation from the AD7175-8, and Figure 3 Figure 70. SPI Write Transaction with CRC shows the timing for a write operation to the AD7175-8. It is
UP TO 8-BIT COMMAND 32-BIT OUTPUT 8-BIT CRC
possible to read from the data register several times even though
CS
the RDY output returns high after the first read operation. However, care must be taken to ensure that the read operations are completed before the next output update occurs. In continuous
CMD DIN
read mode, the data register can be read only once. The serial interface can operate in 3-wire mode by tying CS low.
DOUT/ DATA CRC RDY
In this case, the SCLK, DIN, and DOUT/RDY pins are used to communicate with the AD7175-8. The end of the conversion
SCLK
can also be monitored using the RDY bit in the status register. 075 12911- The AD7175-8 can be reset by writing 64 SCLKs with CS = 0 Figure 71. SPI Read Transaction with CRC and DIN = 1. A reset returns the interface to the state in which it expects a write to the communications register. This operation If checksum protection is enabled when continuous read mode resets the contents of al registers to their power-on values. is active, an implied read data command of 0x44 before every Following a reset, allow a period of 500 µs before addressing the data transmission must be accounted for when calculating the serial interface. checksum value. This implied read data command ensures a nonzero checksum value even if the ADC data equals 0x000000.
CHECKSUM PROTECTION
The AD7175-8 has a checksum mode that can be used to improve interface robustness. Using the checksum ensures that only valid data is written to a register and allows data read from a register to be validated. If an error occurs during a register write, the CRC_ERROR bit is set in the status register. However, to ensure that the register write is successful, read back the register and verify the checksum. Rev. 0 | Page 40 of 64 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES DIGITAL COMMUNICATION Accessing the ADC Register Map AD7175-8 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Gain Registers Offset Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION BUFFERED ANALOG INPUT CROSSPOINT MULTIPLEXER Fully Differential Inputs Single-Ended Inputs AD7175-8 REFERENCE External Reference Internal Reference BUFFERED REFERENCE INPUT CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER SINGLE CYCLE SETTLING ENHANCED 50 HZ AND 60 HZ REJECTION FILTERS OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE I/O EXTERNAL MULTIPLEXER CONTROL DELAY 16-BIT/24-BIT CONVERSIONS DOUT_RESET SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR Input/Output DATA_STAT IOSTRENGTH POWER-DOWN SWITCH INTERNAL TEMPERATURE SENSOR GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 15 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 7 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 7 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 7 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 7 OUTLINE DIMENSIONS ORDERING GUIDE