Datasheet AD9645 (Analog Devices) - 31

AD9645 Data Sheet MEMORY MAP REGISTER TABLE
The AD9645 uses a 3-wire interface and 16-bit addressing and, When Bit 5 in Register 0x00 is set high, the SPI enters a soft therefore, Bit 0 and Bit 7 in Register 0x00 are set to 0, and Bit 3 reset, where al of the user registers revert to their default values and Bit 4 are set to 1. and Bit 2 is automatically cleared.
Table 16. Default Addr. Parameter Bit 7 Bit 0 Value (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments
Chip Configuration Registers 0x00 SPI port 0 = SDO LSB first Soft reset 1 = 16-bit 1 = 16-bit Soft reset LSB first 0 = SDO 0x18 Nibbles are configuration active address address active mirrored to allow a given register value to perform the same function for either MSB- first or LSB- first mode. 0x01 Chip ID (global) 8-bit chip ID, Bits[7:0] 0x8B Unique chip AD9645 0x8B = dual, 14-bit, 80 MSPS/125 MSPS, serial LVDS ID used to differentiate devices; read only. 0x02 Chip grade Open Speed grade ID, Bits[6:4] Open Open Open Open Unique speed (global) 100 = 80 MSPS grade ID used 110 = 125 MSPS to differentiate graded devices; read only. Device Index and Transfer Registers 0x05 Device index Open Open Clock Clock Open Open Data Data 0x33 Bits are set to Channel Channel Channel B Channel A determine DCO FCO which device on chip receives the next write command. Default is all devices on chip. 0xFF Transfer Open Open Open Open Open Open Open Initiate 0x00 Set override resolution/ sample rate override. Global ADC Function Registers 0x08 Power modes Open Open Open Open Open Open Power mode 0x00 Determines (global) 00 = chip run various 01 = full power-down generic 10 = standby modes of chip 11 = reset operation. 0x09 Clock (global) Open Open Open Open Open Open Open Duty cycle 0x00 Turns stabilizer duty cycle 0 = off stabilizer on 1 = on or off. 0x0B Clock divide Open Open Open Open Open Clock divide ratio[2:0] 0x00 (global) 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 0x0C Enhancement Open Open Open Open Open Chop Open Open 0x00 Enables/ control mode disables 0 = off chop mode. 1 = on Rev. B | Page 30 of 36 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9645-80 AD9645-125 EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS AND TIMING SDIO/PDWN Pin SCLK/DFS Pin CSB Pin RBIAS Pin OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Device Index (Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:2]—Open Bits[1:0]—Power Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—Open Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Driver Termination Bits[3:1]—Open Bit 0—Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Serial Output Data Control (Register 0x21) Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND GUIDELINES CLOCK STABILITY CONSIDERATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS VCM REFERENCE DECOUPLING SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE