Datasheet AD9613 (Analog Devices) - 34

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AD9613 Data Sheet MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 14 are not currently supported for this device.
Table 14. Memory Map Registers Default Default Addr Register Bit 7 Bit 0 Value Notes/ (Hex) Name (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) (Hex) Comments
Chip Configuration Registers 0x00 SPI port 0 LSB first Soft reset 1 1 Soft reset LSB first 0 0x18 The nibbles configuration are mirrored (global)1 so that LSB- first mode or MSB-first mode registers correctly, regardless of shift mode 0x01 Chip ID 8-bit chip ID[7:0] (AD9613 = 0x83) 0x83 Read only (global) (default) 0x02 Chip grade Open Open Speed grade ID Open Open Open Open Speed (global) 00 = 250 MSPS grade ID 01 = 210 MSPS used to 11 = 170 MSPS differentiate devices; read only Channel Index and Transfer Registers 0x05 Channel index Open Open Open Open Open Open ADC B ADC A 0x03 Bits are set (global) (default) (default) to determine which device on the chip receives the next write command; applies to local registers only 0xFF Transfer Open Open Open Open Open Open Open Transfer 0x00 Synchron- (global) ously transfers data from the master shift register to the slave ADC Functions 0x08 Power modes Open Open External Open Open Open Internal power-down mode 0x00 Determines (local) power- (local) various down pin 00 = normal operation generic function 01 = full power-down modes of (local) 10 = standby chip 0 = power- 11 = reserved operation down 1 = standby 0x09 Global clock Open Open Open Open Open Open Open Duty cycle 0x01 (global) stabilizer (default) 0x0B Clock divide Open Open Input clock divider phase adjust Clock divide ratio 0x00 Clock divide (global) 000 = no delay 000 = divide by 1 values other 001 = 1 input clock cycle 001 = divide by 2 than 000 010 = 2 input clock cycles 010 = divide by 3 auto- 011 = 3 input clock cycles 011 = divide by 4 matically 100 = 4 input clock cycles 100 = divide by 5 cause the 101 = 5 input clock cycles 101 = divide by 6 duty cycle 110 = 6 input clock cycles 110 = divide by 7 stabilizer to 111 = 7 input clock cycles 111 = divide by 8 become active Rev. D | Page 32 of 36 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS ADC DC SPECIFICATIONS ADC AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) ADC OVERRANGE (OR) CHANNEL/CHIP SYNCHRONIZATION SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Transfer Register Map Channel Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTION Sync Control (Register 0x3A) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Buffer Enable APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations VCM SPI Port OUTLINE DIMENSIONS ORDERING GUIDE