Datasheet AD7607 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | 8-Channel DAS with 14-Bit, Bipolar, Simultaneous Sampling ADC |
| Pages / Page | 33 / 9 — AD7607. Data Sheet. Limit at TMIN, TMAX. Parameter. Min. Typ. Max. Unit. … |
| Revision | D |
| File Format / Size | PDF / 884 Kb |
| Document Language | English |
AD7607. Data Sheet. Limit at TMIN, TMAX. Parameter. Min. Typ. Max. Unit. Description. Timing Diagrams. CONVST A,. CONVST B. tCYCLE. tCONV. BUSY
Model Line for this Datasheet
Text Version of Document
AD7607 Data Sheet Limit at TMIN, TMAX Parameter Min Typ Max Unit Description
t27 Delay from RD falling edge to FRSTDATA low 19 ns VDRIVE = 3.3 V to 5.25 V 24 ns VDRIVE = 2.3 V to 2.7 V t28 Delay from 16th SCLK falling edge to FRSTDATA low 17 ns VDRIVE = 3.3 V to 5.25 V 22 ns VDRIVE = 2.3 V to 2.7 V t29 24 ns Delay from CS rising edge until FRSTDATA three-state enabled 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V. 2 The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <3 LSB performance matching between channel sets. 3 A buffer, which is equivalent to a load of 20 pF on the output pins, is used on the data output pins for these measurements.
Timing Diagrams t5 CONVST A, CONVST B tCYCLE t2 CONVST A, CONVST B t3 tCONV t1 BUSY t4 CS t7 tRESET RESET
002 08096- Figure 2. CONVST Timing—Reading After a Conversion
t5 CONVST A, CONVST B tCYCLE t2 CONVST A, CONVST B t3 tCONV t1 BUSY t6 CS t7 tRESET RESET
003 08096- Figure 3. CONVST Timing—Reading During a Conversion
CS t9 t8 t t 11 10 RD t16 t13 t t 14 t 17 15 DATA: DB[15:0] INVALID V1 V2 V3 V4 V7 V8 t26 t27 t29 t24
004
FRSTDATA
08096- Figure 4. Parallel Mode, Separate CS and RD Pulses Rev. C | Page 8 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CONVERTER DETAILS ANALOG INPUT Analog Input Ranges Analog Input Impedance Analog Input Clamp Protection Analog Input Antialiasing Filter Track-and-Hold Amplifiers ADC TRANSFER FUNCTION INTERNAL/EXTERNAL REFERENCE External Reference Mode Internal Reference Mode TYPICAL CONNECTION DIAGRAM POWER-DOWN MODES CONVERSION CONTROL Simultaneous Sampling on All Analog Input Channels Simultaneously Sampling Two Sets of Channels DIGITAL INTERFACE PARALLEL INTERFACE (/SER/BYTE SEL = 0) PARALLEL BYTE INTERFACE (/SER/BYTE SEL = 1, DB15 = 1) SERIAL INTERFACE (/SER/BYTE SEL = 1) READING DURING CONVERSION DIGITAL FILTER LAYOUT GUIDELINES OUTLINE DIMENSIONS ORDERING GUIDE NOTES
t27 Delay from RD falling edge to FRSTDATA low 19 ns VDRIVE = 3.3 V to 5.25 V 24 ns VDRIVE = 2.3 V to 2.7 V t28 Delay from 16th SCLK falling edge to FRSTDATA low 17 ns VDRIVE = 3.3 V to 5.25 V 22 ns VDRIVE = 2.3 V to 2.7 V t29 24 ns Delay from CS rising edge until FRSTDATA three-state enabled 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V. 2 The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <3 LSB performance matching between channel sets. 3 A buffer, which is equivalent to a load of 20 pF on the output pins, is used on the data output pins for these measurements.
Timing Diagrams t5 CONVST A, CONVST B tCYCLE t2 CONVST A, CONVST B t3 tCONV t1 BUSY t4 CS t7 tRESET RESET
002 08096- Figure 2. CONVST Timing—Reading After a Conversion
t5 CONVST A, CONVST B tCYCLE t2 CONVST A, CONVST B t3 tCONV t1 BUSY t6 CS t7 tRESET RESET
003 08096- Figure 3. CONVST Timing—Reading During a Conversion
CS t9 t8 t t 11 10 RD t16 t13 t t 14 t 17 15 DATA: DB[15:0] INVALID V1 V2 V3 V4 V7 V8 t26 t27 t29 t24
004
FRSTDATA
08096- Figure 4. Parallel Mode, Separate CS and RD Pulses Rev. C | Page 8 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CONVERTER DETAILS ANALOG INPUT Analog Input Ranges Analog Input Impedance Analog Input Clamp Protection Analog Input Antialiasing Filter Track-and-Hold Amplifiers ADC TRANSFER FUNCTION INTERNAL/EXTERNAL REFERENCE External Reference Mode Internal Reference Mode TYPICAL CONNECTION DIAGRAM POWER-DOWN MODES CONVERSION CONTROL Simultaneous Sampling on All Analog Input Channels Simultaneously Sampling Two Sets of Channels DIGITAL INTERFACE PARALLEL INTERFACE (/SER/BYTE SEL = 0) PARALLEL BYTE INTERFACE (/SER/BYTE SEL = 1, DB15 = 1) SERIAL INTERFACE (/SER/BYTE SEL = 1) READING DURING CONVERSION DIGITAL FILTER LAYOUT GUIDELINES OUTLINE DIMENSIONS ORDERING GUIDE NOTES
