Datasheet AD7764 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 24-Bit, 312 kSPS, 109 dB Sigma-Delta ADC with On-Chip Buffers and Serial Interface |
| Pages / Page | 34 / 10 — Data Sheet. AD7764. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. INA–. … |
| Revision | C |
| File Format / Size | PDF / 936 Kb |
| Document Language | English |
Data Sheet. AD7764. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. INA–. AVDD3. OUTA+. VREF+. INA+. REFGND. OUTA–. AVDD4. IN–. AVDD1. IN+. AGND1
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Data Sheet AD7764 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V 1 28 INA– AVDD3 V 2 27 OUTA+ VREF+ V 3 26 INA+ REFGND V 4 25 OUTA– AVDD4 V 5 24 IN– AVDD1 V 6 AD7764 23 IN+ AGND1 AV 7 TOP VIEW 22 DD2 RBIAS (Not to Scale) AGND3 8 21 AVDD2 OVERRANGE 9 20 AGND2 SCO 10 19 MCLK FSO 11 18 DEC_RATE SDO 12 17 DVDD SDI 13 16 RESET/PWRDWN
005
FSI 14 15 SYNC
06518- Figure 5. Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1 VINA− Negative Input to the Differential Amplifier. 2 VOUTA+ Positive Output from the Differential Amplifier. 3 VINA+ Positive Input to the Differential Amplifier. 4 VOUTA− Negative Output from the Differential Amplifier. 5 VIN− Negative Input to the Modulator. 6 VIN+ Positive Input to the Modulator. 7, 21 AVDD2 5 V Power Supply. Decouple Pin 7 to AGND3 (Pin 8) with a 100 nF capacitor. Decouple Pin 21 to AGND1 (Pin 23) with a 100 nF capacitor. 8 AGND3 Power Supply Ground for the Analog Circuitry. 9 OVERRANGE Overrange Pin. This pin outputs a logic high to indicate that the user applied an analog input that is approaching the limit of the analog input to the modulator. 10 SCO Serial Clock Out. This clock signal is derived from the internal ICLK signal. The frequency of this clock is equal to ICLK. See the Clocking the AD7764 section for more information. 11 FSO Frame Sync Out. This signal frames the serial data output and is 32 SCO periods wide. 12 SDO Serial Data Out. Data and status are output on this pin during each serial transfer. Each bit is clocked out on an SCO rising edge and is valid on the falling edge. See the AD7764 Serial Interface section for further details. 13 SDI Serial Data In. The first data bit (MSB) must be valid on the next SCO falling edge after the FSI event is latched. Thirty-two bits are required for each write; the first 16-bit word contains the device and register address, and the second word contains the data. See the AD7764 Serial Interface section for more information. 14 FSI Frame Sync Input. The status of this pin is checked on the falling edge of SCO. If this pin is low, then the first data bit is latched in on the next SCO falling edge. See the AD7764 Serial Interface section for more information. 15 SYNC Synchronization Input. A falling edge on this pin resets the internal filter. Use this pin to synchronize multiple devices in a system. See the Synchronization section for more information. 16 RESET/PWRD WN Reset/Power-Down Pin. When a logic low is sensed on this pin, the device is powered down and all internal circuitry is reset. 17 DVDD 2.5 V Power Supply for the Digital Circuitry and FIR Filter. Decouple this pin to the ground plane with a 100 nF capacitor. 18 DEC_RATE Decimation Rate Pin. This pin selects one of the three decimation rate modes. When 2.5 V is applied to this pin, a decimation rate of 64× is selected. Select a decimation rate of 128× by leaving this pin floating. Select a decimation rate of 256× by setting this pin to ground. 19 MCLK Master Clock Input. A low jitter digital clock must be applied to this pin. The output data rate depends on the frequency of this clock. See the Clocking the section for more information. 20 AGND2 Power Supply Ground for the Analog Circuitry. 22 RBIAS Bias Current Setting Pin. This pin must be decoupled to the ground plane. For more information, see the Bias Resistor Selection section. Rev. B | Page 9 of 33 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION Σ-Δ MODULATION AND DIGITAL FILTERING AD7764 ANTIALIAS PROTECTION INPUT STRUCTURE ON-CHIP DIFFERENTIAL AMPLIFIER MODULATOR INPUT STRUCTURE DRIVING THE MODULATOR INPUTS DIRECTLY AD7764 SERIAL INTERFACE READING DATA READING STATUS AND OTHER REGISTERS WRITING TO THE AD7764 FUNCTIONALITY SYNCHRONIZATION OVERRANGE ALERTS POWER MODES Low Power Mode RESETB/PWRDWNB Mode DECIMATION RATE PIN DAISY-CHAINING READING DATA IN DAISY-CHAIN MODE WRITING DATA IN DAISY-CHAIN MODE CLOCKING THE AD7764 MCLK JITTER REQUIREMENTS Example 1 Example 2 DECOUPLING AND LAYOUT INFORMATION SUPPLY DECOUPLING REFERENCE VOLTAGE FILTERING DIFFERENTIAL AMPLIFIER COMPONENTS LAYOUT CONSIDERATIONS USING THE AD7764 BIAS RESISTOR SELECTION AD7764 REGISTERS CONTROL REGISTER STATUS REGISTER GAIN REGISTER—ADDRESS 0x0004 Nonbit Mapped, Default Value: 0xA000 OVERRANGE REGISTER—ADDRESS 0x0005 Nonbit Mapped, Default Value: 0xCCCC OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet AD7764 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V 1 28 INA– AVDD3 V 2 27 OUTA+ VREF+ V 3 26 INA+ REFGND V 4 25 OUTA– AVDD4 V 5 24 IN– AVDD1 V 6 AD7764 23 IN+ AGND1 AV 7 TOP VIEW 22 DD2 RBIAS (Not to Scale) AGND3 8 21 AVDD2 OVERRANGE 9 20 AGND2 SCO 10 19 MCLK FSO 11 18 DEC_RATE SDO 12 17 DVDD SDI 13 16 RESET/PWRDWN
005
FSI 14 15 SYNC
06518- Figure 5. Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1 VINA− Negative Input to the Differential Amplifier. 2 VOUTA+ Positive Output from the Differential Amplifier. 3 VINA+ Positive Input to the Differential Amplifier. 4 VOUTA− Negative Output from the Differential Amplifier. 5 VIN− Negative Input to the Modulator. 6 VIN+ Positive Input to the Modulator. 7, 21 AVDD2 5 V Power Supply. Decouple Pin 7 to AGND3 (Pin 8) with a 100 nF capacitor. Decouple Pin 21 to AGND1 (Pin 23) with a 100 nF capacitor. 8 AGND3 Power Supply Ground for the Analog Circuitry. 9 OVERRANGE Overrange Pin. This pin outputs a logic high to indicate that the user applied an analog input that is approaching the limit of the analog input to the modulator. 10 SCO Serial Clock Out. This clock signal is derived from the internal ICLK signal. The frequency of this clock is equal to ICLK. See the Clocking the AD7764 section for more information. 11 FSO Frame Sync Out. This signal frames the serial data output and is 32 SCO periods wide. 12 SDO Serial Data Out. Data and status are output on this pin during each serial transfer. Each bit is clocked out on an SCO rising edge and is valid on the falling edge. See the AD7764 Serial Interface section for further details. 13 SDI Serial Data In. The first data bit (MSB) must be valid on the next SCO falling edge after the FSI event is latched. Thirty-two bits are required for each write; the first 16-bit word contains the device and register address, and the second word contains the data. See the AD7764 Serial Interface section for more information. 14 FSI Frame Sync Input. The status of this pin is checked on the falling edge of SCO. If this pin is low, then the first data bit is latched in on the next SCO falling edge. See the AD7764 Serial Interface section for more information. 15 SYNC Synchronization Input. A falling edge on this pin resets the internal filter. Use this pin to synchronize multiple devices in a system. See the Synchronization section for more information. 16 RESET/PWRD WN Reset/Power-Down Pin. When a logic low is sensed on this pin, the device is powered down and all internal circuitry is reset. 17 DVDD 2.5 V Power Supply for the Digital Circuitry and FIR Filter. Decouple this pin to the ground plane with a 100 nF capacitor. 18 DEC_RATE Decimation Rate Pin. This pin selects one of the three decimation rate modes. When 2.5 V is applied to this pin, a decimation rate of 64× is selected. Select a decimation rate of 128× by leaving this pin floating. Select a decimation rate of 256× by setting this pin to ground. 19 MCLK Master Clock Input. A low jitter digital clock must be applied to this pin. The output data rate depends on the frequency of this clock. See the Clocking the section for more information. 20 AGND2 Power Supply Ground for the Analog Circuitry. 22 RBIAS Bias Current Setting Pin. This pin must be decoupled to the ground plane. For more information, see the Bias Resistor Selection section. Rev. B | Page 9 of 33 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION Σ-Δ MODULATION AND DIGITAL FILTERING AD7764 ANTIALIAS PROTECTION INPUT STRUCTURE ON-CHIP DIFFERENTIAL AMPLIFIER MODULATOR INPUT STRUCTURE DRIVING THE MODULATOR INPUTS DIRECTLY AD7764 SERIAL INTERFACE READING DATA READING STATUS AND OTHER REGISTERS WRITING TO THE AD7764 FUNCTIONALITY SYNCHRONIZATION OVERRANGE ALERTS POWER MODES Low Power Mode RESETB/PWRDWNB Mode DECIMATION RATE PIN DAISY-CHAINING READING DATA IN DAISY-CHAIN MODE WRITING DATA IN DAISY-CHAIN MODE CLOCKING THE AD7764 MCLK JITTER REQUIREMENTS Example 1 Example 2 DECOUPLING AND LAYOUT INFORMATION SUPPLY DECOUPLING REFERENCE VOLTAGE FILTERING DIFFERENTIAL AMPLIFIER COMPONENTS LAYOUT CONSIDERATIONS USING THE AD7764 BIAS RESISTOR SELECTION AD7764 REGISTERS CONTROL REGISTER STATUS REGISTER GAIN REGISTER—ADDRESS 0x0004 Nonbit Mapped, Default Value: 0xA000 OVERRANGE REGISTER—ADDRESS 0x0005 Nonbit Mapped, Default Value: 0xCCCC OUTLINE DIMENSIONS ORDERING GUIDE
