Datasheet AD9252 (Analog Devices) - 32

Data Sheet AD9252 Default Addr. (MSB) (LSB) Value Notes/ (Hex) Parameter Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Hex) Comments
14 output_mode X 0 = LVDS X X X Output 00 = offset binary 0x00 Configures the ANSI-644 invert (default) outputs and the (default) 1 = on 01 = twos complement format of the data. 1 = LVDS 0 = off low power, (default) (IEEE 1596.3 similar) 15 output_adjust X X Output driver X X X DCO and 0x00 Determines termination FCO LVDS or other 00 = none (default) 2× drive output properties. 01 = 200 Ω strength Primarily func- 10 = 100 Ω 1 = on tions to set the 11 = 100 Ω 0 = off LVDS span and (default) common-mode levels in place of an external resistor. 16 output_phase X X X X 0011 = output clock phase adjust 0x03 On devices that (0000 through 1010) utilize global 0000 = 0° relative to data edge clock divide, 0001 = 60° relative to data edge this register 0010 = 120° relative to data edge determines 0011 = 180° relative to data edge (default) which phase 0101 = 300° relative to data edge of the divider 0110 = 360° relative to data edge output is used 1000 = 480° relative to data edge to supply the 1001 = 540° relative to data edge output clock. 1010 = 600° relative to data edge Internal latching 1011 to 1111 = 660° relative to data edge is unaffected. 19 user_patt1_lsb B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 1 LSB. 1A user_patt1_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined pattern, 1 MSB. 1B user_patt2_lsb B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 2 LSB. 1C user_patt2_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined pattern, 2 MSB. 21 serial_control LSB first X X X <10 000 = 14 bits (default, normal bit 0x00 Serial stream 1 = on MSPS, stream) control. Default 0 = off low 001 = 8 bits causes MSB first (default) encode 010 = 10 bits and the native rate 011 = 12 bits bit stream mode 100 = 14 bits (global). 1 = on 0 = off (default) 22 serial_ch_stat X X X X X X Channel Channel 0x00 Used to power output power- down individual reset down sections of a 1 = on 1 = on converter (local). 0 = off 0 = off (default) (default) 1 X = an undefined feature. Rev. E | Page 31 of 52 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Absolute Maximum Ratings Thermal Impedance ESD Caution Pin Configuration and Function Descriptions Equivalent Circuits Typical Performance Characteristics Theory of Operation Analog Input Considerations Differential Input Configurations Single-Ended Input Configuration Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/ODM Pin SCLK/DTP Pin CSB Pin RBIAS Pin Voltage Reference Internal Reference Operation External Reference Operation Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations Evaluation Board Power Supplies Input Signals Output Signals Default Operation and Jumper Selection Settings Alternative Analog Input Drive Configuration Outline Dimensions Ordering Guide