Datasheet AD9229 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | Quad 12-Bit, 50/65 MSPS, Serial LVDS A/D Converter |
| Pages / Page | 41 / 4 — AD9229. SPECIFICATIONS. Table 1. AD9229-50. AD9229-65. Test. Parameter … |
| Revision | B |
| File Format / Size | PDF / 799 Kb |
| Document Language | English |
AD9229. SPECIFICATIONS. Table 1. AD9229-50. AD9229-65. Test. Parameter Temperature. Level Min Typ. Max Min Typ. Max Unit
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AD9229 SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 3.0 V, maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless otherwise noted.
Table 1. AD9229-50 AD9229-65 Test Parameter Temperature Level Min Typ Max Min Typ Max Unit
RESOLUTION 12 12 Bits ACCURACY No Missing Codes Full VI Guaranteed Guaranteed Offset Error Full VI ±5 ±25 ±5 ±25 mV Offset Matching Full VI ±5 ±25 ±5 ±25 mV Gain Error1 Full VI ±0.3 ±2.5 ±0.3 ±2.5 % FS Gain Matching1 Full VI ±0.2 ±1.5 ±0.2 ±1.5 % FS Differential Nonlinearity (DNL) 25°C V ±0.3 ±0.3 LSB Full VI ±0.3 ±0.6 ±0.3 ±0.7 LSB Integral Nonlinearity (INL) 25°C V ±0.6 ±0.4 LSB Full VI ±0.6 ±1 ±0.4 ±1 LSB TEMPERATURE DRIFT Offset Error Full V ±2 ±3 ppm/°C Gain Error1 Full V ±12 ±12 ppm/°C Reference Voltage, VREF = 1 V Full V ±16 ±16 ppm/°C REFERENCE Output Voltage Error, VREF = 1 V Full VI ±10 ±30 ±10 ±30 mV Load Regulation @ 1.0 mA, VREF = 1 V Full V 3 3 mV Output Voltage Error, VREF = 0.5 V Full VI ±8 ±17 ±8 ±17 mV Load Regulation @ 0.5 mA, Full V 0.2 0.2 mV VREF = 0.5 V Input Resistance Full V 7 7 kΩ ANALOG INPUTS Differential Input Voltage Range Full VI 2 2 V p-p VREF = 1 V Differential Input Voltage Range Full VI 1 1 V p-p VREF = 0.5 V Common Mode Voltage Full V 1.5 1.5 V Input Capacitance2 Full V 7 7 pF Analog Bandwidth, Full Power Full V 400 400 MHz POWER SUPPLY AVDD Full IV 2.7 3.0 3.6 2.7 3.0 3.6 V DRVDD Full IV 2.7 3.0 3.6 2.7 3.0 3.6 V IAVDD Full VI 300 330 420 455 mA DRVDD Full VI 28 31 29 33 mA Power Dissipation3 Full VI 985 1083 1350 1465 mW Power-Down Dissipation Full V 3 3 mW CROSSTALK4 Full V –95 –95 dB 1 Gain error and gain temperature coefficients are based on the ADC only, with a fixed 1.0 V external reference and a 2 V p-p differential analog input. 2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 4 for the equivalent analog input structure. 3 Power dissipation measured with rated encode and 2.4 MHz analog input at –0.5 dBFS. 4 Typical specification over the first Nyquist zone. Rev. B | Page 3 of 40 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Differential Input Configurations Single-Ended Input Configuration CLOCK INPUT CONSIDERATIONS Power Dissipation and Power-Down Mode Digital Outputs Timing DTP Pin Voltage Reference Internal Reference Connection External Reference Operation Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations EVALUATION BOARD POWER SUPPLIES INPUT SIGNALS OUTPUT SIGNALS DEFAULT OPERATION AND JUMPER SELECTION SETTINGS ALTERNATE ANALOG INPUT DRIVE CONFIGURATION OUTLINE DIMENSIONS ORDERING GUIDE
AD9229 SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 3.0 V, maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless otherwise noted.
Table 1. AD9229-50 AD9229-65 Test Parameter Temperature Level Min Typ Max Min Typ Max Unit
RESOLUTION 12 12 Bits ACCURACY No Missing Codes Full VI Guaranteed Guaranteed Offset Error Full VI ±5 ±25 ±5 ±25 mV Offset Matching Full VI ±5 ±25 ±5 ±25 mV Gain Error1 Full VI ±0.3 ±2.5 ±0.3 ±2.5 % FS Gain Matching1 Full VI ±0.2 ±1.5 ±0.2 ±1.5 % FS Differential Nonlinearity (DNL) 25°C V ±0.3 ±0.3 LSB Full VI ±0.3 ±0.6 ±0.3 ±0.7 LSB Integral Nonlinearity (INL) 25°C V ±0.6 ±0.4 LSB Full VI ±0.6 ±1 ±0.4 ±1 LSB TEMPERATURE DRIFT Offset Error Full V ±2 ±3 ppm/°C Gain Error1 Full V ±12 ±12 ppm/°C Reference Voltage, VREF = 1 V Full V ±16 ±16 ppm/°C REFERENCE Output Voltage Error, VREF = 1 V Full VI ±10 ±30 ±10 ±30 mV Load Regulation @ 1.0 mA, VREF = 1 V Full V 3 3 mV Output Voltage Error, VREF = 0.5 V Full VI ±8 ±17 ±8 ±17 mV Load Regulation @ 0.5 mA, Full V 0.2 0.2 mV VREF = 0.5 V Input Resistance Full V 7 7 kΩ ANALOG INPUTS Differential Input Voltage Range Full VI 2 2 V p-p VREF = 1 V Differential Input Voltage Range Full VI 1 1 V p-p VREF = 0.5 V Common Mode Voltage Full V 1.5 1.5 V Input Capacitance2 Full V 7 7 pF Analog Bandwidth, Full Power Full V 400 400 MHz POWER SUPPLY AVDD Full IV 2.7 3.0 3.6 2.7 3.0 3.6 V DRVDD Full IV 2.7 3.0 3.6 2.7 3.0 3.6 V IAVDD Full VI 300 330 420 455 mA DRVDD Full VI 28 31 29 33 mA Power Dissipation3 Full VI 985 1083 1350 1465 mW Power-Down Dissipation Full V 3 3 mW CROSSTALK4 Full V –95 –95 dB 1 Gain error and gain temperature coefficients are based on the ADC only, with a fixed 1.0 V external reference and a 2 V p-p differential analog input. 2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 4 for the equivalent analog input structure. 3 Power dissipation measured with rated encode and 2.4 MHz analog input at –0.5 dBFS. 4 Typical specification over the first Nyquist zone. Rev. B | Page 3 of 40 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Differential Input Configurations Single-Ended Input Configuration CLOCK INPUT CONSIDERATIONS Power Dissipation and Power-Down Mode Digital Outputs Timing DTP Pin Voltage Reference Internal Reference Connection External Reference Operation Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations EVALUATION BOARD POWER SUPPLIES INPUT SIGNALS OUTPUT SIGNALS DEFAULT OPERATION AND JUMPER SELECTION SETTINGS ALTERNATE ANALOG INPUT DRIVE CONFIGURATION OUTLINE DIMENSIONS ORDERING GUIDE
