Datasheet AD7934-6 (Analog Devices) - 8

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AD7934-6 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V 1 28 DD VIN3 W/B 2 27 VIN2 DB0 3 26 VIN1 DB1 4 25 VIN0 AD7934-6 DB2 5 24 VREFIN/VREFOUT TOP VIEW DB3 6 (Not to Scale) 23 AGND DB4 7 22 CS DB5 8 21 RD DB6 9 20 WR DB7 10 19 CONVST V 11 18 DRIVE CLKIN DGND 12 17 BUSY DB8/HBEN 13 16 DB11
6 0 0
DB9 14 15 DB10
2- 75 04 Figure 2.
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1 VDD Power Supply Input. The VDD range for the AD7934-6 is from 2.7 V to 5.25 V. The supply should be decoupled to AGND with a 0.1 μF capacitor and a 10 μF tantalum capacitor. 2 W/B Word/Byte Input. When this input is logic high, word transfer mode is enabled, and data is transferred to and from the AD7934-6 in 12-bit words on Pin DB0 to Pin DB11. When W/B is logic low, byte transfer mode is enabled. Data and the channel ID are transferred on Pin DB0 to Pin DB7, and Pin DB8/HBEN assumes its HBEN functionality. When operating in byte transfer mode, unused data lines should be tied off to DGND. 3 to 10 DB0 to DB7 Data Bit 0 to Data Bit 7. Three-state parallel digital I/O pins that provide the conversion result, and allow the control register to be programmed. These pins are controlled by CS, RD, and WR. The logic high/low voltage levels for these pins are determined by the VDRIVE input. 11 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines what voltage the parallel interface of the AD7934-6 operates. This pin should be decoupled to DGND. The voltage at this pin can be different to that at VDD, but should never exceed VDD by more than 0.3 V. 12 DGND Digital Ground. This is the ground reference point for all digital circuitry on the AD7934-6. This pin should connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential, and must not be more than 0.3 V apart, even on a transient basis. 13 DB8/HBEN Data Bit 8/High Byte Enable. When W/B is high, this pin acts as Data Bit 8, a three-state I/O pin that is controlled by CS, RD, and WR. When W/B is low, this pin acts as the high byte enable pin. When HBEN is low, the low byte of data written to or read from the AD7934-6 is on DB0 to DB7. When HBEN is high, the top four bits of the data being written to or read from the AD7934-6 are on DB0 to DB3. When reading from the device, DB4 and DB5 of the high byte contain the ID of the channel corresponding to the conversion result (see the channel address bits in Table 9). DB6 and DB7 are always 0. When writing to the device, DB4 to DB7 of the high byte must all be 0s. 14 to 16 DB9 to DB11 Data Bit 9 to Data Bit 11. Three-state parallel digital I/O pins that provide the conversion result and allow the control register to be programmed in word mode. These pins are controlled by CS, RD, and WR. The logic high/low voltage levels for these pins are determined by the VDRIVE input. 17 BUSY Busy Output. Logic output indicating the status of the conversion. The BUSY output goes high following the falling edge of CONVST and stays high for the duration of the conversion. Once the conversion is complete and the result is available in the output register, the BUSY output goes low. The track-and-hold returns to track mode just prior to the falling edge of BUSY, on the 13th rising edge of CLKIN (see Figure 34). 18 CLKIN Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the AD7934-6 takes 13 clock cycles + t2. The frequency of the master clock input therefore determines the conversion time and achievable throughput rate. The CLKIN signal can be a continuous or burst clock. 19 CONVST Conversion Start Input. A falling edge on CONVST is used to initiate a conversion. The track-and-hold goes from track to hold mode on the falling edge of CONVST, and the conversion process is initiated at this point. Following power-down, when operating in the autoshutdown or autostandby mode, a rising edge on CONVST is used to power up the device. 20 WR Write Input. Active low logic input used in conjunction with CS to write data to the control register. 21 RD Read Input. Active low logic input used in conjunction with CS to access the conversion result. The conversion result is placed on the data bus following the falling edge of RD read while CS is low. Rev. B | Page 7 of 28 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY CONTROL REGISTER SEQUENCER OPERATION Writing to the Control Register to Program the Sequencer CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT STRUCTURE ANALOG INPUT CONFIGURATIONS Single-Ended Mode Differential Mode Driving Differential Inputs Using an Op Amp Pair Pseudo Differential Mode ANALOG INPUT SELECTION Traditional Multichannel Operation (SEQ0 = SEQ1 = 0) Using the Sequencer: Consecutive Sequence (SEQ0 = SEQ1 = 1) REFERENCE Digital Inputs VDRIVE Input PARALLEL INTERFACE Reading Data from the AD7934-6 Writing Data to the AD7934-6 POWER MODES OF OPERATION Normal Mode (PM1 = PM0 = 0) Autoshutdown Mode (PM1 = 0; PM0 = 1) Autostandby Mode (PM1 = 1; PM0 = 0) Full Shutdown Mode (PM1 = 1; PM0 = 1) POWER vs. THROUGHPUT RATE MICROPROCESSOR INTERFACING AD7934-6 to ADSP-21xx Interface AD7934-6 to ADSP-21065L Interface AD7934-6 to TMS32020, TMS320C25, and TMS320C5x Interface AD7934-6 to 80C186 Interface APPLICATION HINTS GROUNDING AND LAYOUT EVALUATING THE AD7934-6 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE