Datasheet AD7997, AD7998 (Analog Devices) - 20

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AD7997/AD7998 CONVERSION RESULT REGISTER DATAHIGH Register CH1/CH2/CH3/CH4
The conversion result register is a 16-bit, read-only register that The DATAHIGH registers for CH1 to CH 4 are 16-bit read/write stores the conversion result from the ADC in straight binary registers; only the 12 LSBs of each register are used. This format. A 2-byte read is necessary to read data from this register. register stores the upper limit that activates the ALERT output Table 13 shows the contents of the first byte to be read from the and/or the Alert_Flag bit in the conversion result register. If the AD7997/AD7998, and Table 14 shows the contents of the second value in the conversion result register is greater than the value byte to be read. in the DATAHIGH register, an ALERT occurs for that channel. When the conversion result returns to a value at least N LSBs
Table 13. Conversion Value Register (First Read)
below the DATAHIGH register value, the ALERT output pin and
D15 D14 D13 D12 D11 D10 D9 D8
Alert_Flag bit are reset. The value of N is taken from the Alert_Flag CH ID2 CH ID1 CH ID0 M S B B10 B9 B8 hysteresis register associated with that channel. The ALERT pin can also be reset by writing to Bits D2 and D1 in the
Table 14. Conversion Value Register (Second Read)
configuration register. For the AD7997, D1 and D0 of the
D7 D6 D5 D4 D3 D2 D1 D0
DATAHIGH register should contain 0s. B7 B6 B5 B4 B3 B2 B1 B0
Table 15. DATA HIGH Register (First Read/Write) D15 D14 D13 D12 D11 D10 D9 D8
The AD7997/AD7998 conversion result consists of an Alert_Flag 0 0 0 0 B11 B10 B9 B8 bit, three channel identifier bits, and the 10- and 12-bit data result (MSB first). For the AD7997, the 2 LSBs (D1 and D0) of
Table 16. DATAHIGH Register (Second Read/Write)
the second read contain two 0s. The three channel identification
D7 D6 D5 D4 D3 D2 D1 D0
bits can be used to identify to which of the eight analog input B7 B6 B5 B4 B3 B2 B1 B0 channels the conversion result corresponds. The Alert_Flag bit indicates whether the conversion result being
DATALOW Register CH1/CH2/CH3/CH4
read or any other channel result has violated the limit registers The DATALOW register for each channel is a 16-bit read/write associated with it. If an ALERT occurs, the master can read the register; only the 12 LSBs of each register are used. The register ALERT status register to obtain more information on where the stores the lower limit that activates the ALERT output and/or ALERT occurred. the Alert_Flag bit in the conversion result register. If the value in the conversion result register is less than the value in the
LIMIT REGISTERS
DATALOW register, an ALERT occurs for that channel. When the The AD7997/AD7998 have four pairs of limit registers. Each conversion result returns to a value at least N LSBs above the pair stores high and low conversion limits for the first four DATALOW register value, the ALERT output pin and Alert_Flag analog input channels, CH1 to CH4. Each pair of limit registers bit are reset. The value of N is taken from the hysteresis register has one associated hysteresis register. All 12 registers are 16 bits associated with that channel. The ALERT output pin can also be wide; only the 12 LSBs of the registers are used for the AD7997 reset by writing to Bits D2 and D1 in the configuration register. and AD7998. For the AD7997, the 2 LSBs, D1 and D0 in these For the AD7997, D1 to D0 of the DATALOW register should registers, should contain 0s. On power-up, the contents of the contain 0s. DATAHIGH register for each channel is full scale, while the
Table 17. DATALOW Register (First Read/Write)
contents of the DATALOW registers is zero scale by default. The
D15 D14 D13 D12 D11 D10 D9 D8
AD7997/AD7998 signal an alert (in either hardware, software, 0 0 0 0 B11 B10 B9 B8 or both depending on configuration) if the conversion result moves outside the upper or lower limit set by the limit registers.
Table 18. DATA
There are no limit registers or hysteresis registers associated
LOW Register (Second Read/Write)
with CH5 to CH8.
D7 D6 D5 D4 D3 D2 D1 D0
B7 B6 B5 B4 B3 B2 B1 B0 Rev. 0 | Page 20 of 32 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS AD7997 SPECIFICATIONS AD7998 SPECIFICATIONS I2C TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT INFORMATION CONVERTER OPERATION TYPICAL CONNECTION DIAGRAM ANALOG INPUT INTERNAL REGISTER STRUCTURE ADDRESS POINTER REGISTER CONFIGURATION REGISTER CONVERSION RESULT REGISTER LIMIT REGISTERS DATAHIGH Register CH1/CH2/CH3/CH4 DATALOW Register CH1/CH2/CH3/CH4 Hysteresis Register (CH1/CH2/CH3/CH4) Using the Limit Registers to Store Min/Max Conversion Result ALERT STATUS REGISTER (CH1 TO CH4) CYCLE TIMER REGISTER SAMPLE DELAY AND BIT TRIAL DELAY SERIAL INTERFACE SERIAL BUS ADDRESS WRITING TO THE AD7997/AD7998 WRITING TO THE ADDRESS POINTER REGISTER FOR A SUBSEQUENT REA WRITING A SINGLE BYTE OF DATA TO THE ALERT STATUS REGISTER O WRITING TWO BYTES OF DATA TO A LIMIT, HYSTERESIS, OR CONFIGU READING DATA FROM THE AD7997/AD7998 ALERT/BUSY PIN SMBus ALERT BUSY PLACING THE AD7997-1/AD7998-1 INTOHIGH SPEED MODE THE ADDRESS SELECT (AS) PIN MODES OF OPERATION MODE 1—USING THE PIN MODE 2 – COMMAND MODE MODE 3—AUTOMATIC CYCLE INTERVAL MODE OUTLINE DIMENSIONS ORDERING GUIDE RELATED PARTS IN I2C-COMPATIBLE ADC PRODUCT FAMILY