Datasheet AD7453 (Analog Devices)

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Pseudo Differential, 555 kSPS 12-Bit ADC in an 8-Lead SOT-23 AD7453 FEATURES FUNCTIONAL BLOCK DIAGRAM Specified for VDD of 2.7 V to 5.25 V VDD Low power at max throughput rate: 3.3 mW max at 555 kSPS with VDD = 3 V 7.25 mW max at 555 kSPS with VDD = 5 V Pseudo differential analog input VIN+ 12-BIT Wide input bandwidth: T/H SUCCESSIVE VIN– APPROXIMATION 70 dB SINAD at 100 kHz input frequency ADC VREF Flexible power/serial clock speed management No pipeline delays High speed serial interface: SPI®/QSPI™/MICROWIRE™/DSP compatible SCLK Power-down mode: 1 µA max SDATA AD7453 CONTROL LOGIC 8-lead SOT-23 package CS
-001
APPLICATIONS Transducer interface
03155-A
GND Battery-powered systems Data acquisition systems
Figure 1.
Portable instrumentation PRODUCT HIGHLIGHTS GENERAL DESCRIPTION
1. Operation with 2.7 V to 5.25 V Power Supplies. The AD74531 is a 12-bit, high speed, low power, successive 2. High Throughput with Low Power Consumption. With a approximation (SAR) analog-to-digital converter that features a 3 V supply, the AD7453 offers 3.3 mW max power pseudo differential analog input. This part operates from a consumption for a 555 kSPS throughput rate. single 2.7 V to 5.25 V power supply and features throughput 3. Pseudo Differential Analog Input. rates up to 555 kSPS. 4. Flexible Power/Serial Clock Speed Management. The The part contains a low noise, wide bandwidth, differential conversion rate is determined by the serial clock, allowing track-and-hold amplifier (T/H) that can handle input frequen- the power to be reduced as the conversion time is reduced cies up to 3.5 MHz. The reference voltage for the AD7453 is through the serial clock speed increase. This part also applied externally to the VREF pin and can range from 100 mV to features a shutdown mode to maximize power efficiency at VDD, depending on the power supply and what suits the lower throughput rates. application. 5. Variable Voltage Reference Input. The conversion process and data acquisition are controlled 6. No Pipeline Delay. using CS and the serial clock, allowing the device to interface 7. Accurate control of the sampling instant via a CS input and with microprocessors or DSPs. The input signals are sampled on once-off conversion control. the falling edge of CS; the conversion is also initiated at this point. 8. ENOB > 10 bits Typically with 500 mV Reference. The SAR architecture of this part ensures that there are no pipeline delays. The AD7453 uses advanced design techniques 1Protected by U.S. Patent Number 6,681,332. to achieve very low power dissipation.
Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. or otherwise under any patent or patent rights of Analog Devices. Trademarks and Tel: 781.329.4700 www.analog.com registered trademarks are the property of their respective owners. Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY AD7453–TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM THE ANALOG INPUT Analog Input Structure DIGITAL INPUTS REFERENCE SERIAL INTERFACE Timing Example 1 MODES OF OPERATION NORMAL MODE POWER-DOWN MODE POWER-UP TIME POWER VS. THROUGHPUT RATE MICROPROCESSOR AND DSP INTERFACING AD7453 to ADSP-21xx AD7453 to TMS320C5x/C54x AD7453 to DSP56xxx APPLICATION HINTS Grounding and Layout EVALUATING THE AD7453’S PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE