Datasheet AD7790 (Analog Devices) - 6

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Data Sheet AD7790 TIMING CHARACTERISTICS1, 2 Table 2. (VDD = 2.5 V to 5.25 V; GND = 0 V, REFIN(+) = 2.5 V, REFIN(–) = GND, CDIV1 = CDIV0 = 0, Input Logic 0 = 0 V, Input Logic 1 = VDD, unless otherwise noted.) Limit at TMIN, TMAX Parameter (B Version) Unit Conditions/Comments
t3 100 ns min SCLK High Pulsewidth t4 100 ns min SCLK Low Pulsewidth Read Operation t1 0 ns min CS Falling Edge to DOUT/RDY Active Time 60 ns max VDD = 4.75 V to 5.25 V 80 ns max VDD = 2.5 V to 3.6 V t 3 2 0 ns min SCLK Active Edge to Data Valid Delay4 60 ns max VDD = 4.75 V to 5.25 V 80 ns max VDD = 2.5 V to 3.6 V t 5, 6 5 10 ns min Bus Relinquish Time after CS Inactive Edge 80 ns max t6 100 ns max SCLK Inactive Edge to CS Inactive Edge t7 10 ns min SCLK Inactive Edge to DOUT/RDY High Write Operation t8 0 ns min CS Falling Edge to SCLK Active Edge Setup Time4 t9 30 ns min Data Valid to SCLK Edge Setup Time t10 25 ns min Data Valid to SCLK Edge Hold Time t11 0 ns min CS Rising Edge to SCLK Edge Hold Time 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. 2 See Figure 3 and Figure 4. 3 These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits. 4 SCLK active edge is falling edge of SCLK. 5 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances. 6 RDY returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read only once. Rev. A | Page 5 of 20 Document Outline AD7790—Specifications Timing Characteristics Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics On-Chip Registers Communications Register (RS1, RS0 = 0, 0) Status Register (RS1, RS0 = 0, 0; Power-on/Reset = 0x88) Mode Register (RS1, RS0 = 0, 1; Power-on/Reset = 0x02) Filter Register (RS1, RS0 = 1, 0; Power-on/Reset = 0x04) Data Register (RS1, RS0 = 1, 1; Power-on/Reset = 0x0000) ADC Circuit Information Overview Noise Performance Reduced Current Modes Digital Interface Single Conversion Mode Continuous Conversion Mode Continuous Read Mode Circuit Description Analog Input Channel Programmable Gain Amplifier Bipolar Configuration Data Output Coding Reference Input VDD Monitor Grounding and Layout Outline Dimensions Ordering Guide