Datasheet AD7910, AD7920 (Analog Devices) - 20

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AD7910/AD7920 MICROPROCESSOR INTERFACING
The serial interface on the AD7910/AD7920 allows the parts to
AD7910/AD7920 TO ADSP-218x
be directly connected to a range of different microprocessors. The ADSP-218x family of DSPs is interfaced directly to the This section explains how to interface the AD7910/AD7920 AD7910/AD7920 without any glue logic required. The SPORT with some of the more common microcontroller and DSP serial control register should be set up as follows: interface protocols. TFSW = RFSW = 1, Alternate Framing
AD7910/AD7920 TO TMS320C541 INTERFACE
INVRFS = INVTFS = 1, Active Low Frame Signal The serial interface on the TMS320C541 uses a continuous serial DTYPE = 00, Right Justify Data clock and frame synchronization signals to synchronize the data ISCLK = 1, Internal Serial Clock transfer operations with peripheral devices like the TFSR = RFSR = 1, Frame Every Word AD7910/AD7920. The CS input allows easy interfacing between IRFS = 0, Sets up RFS as an Input the TMS320C541 and the AD7910/AD7920 without any glue logic ITFS = 1, Sets up TFS as an Output required. The serial port of the TMS320C541 is set up to operate in SLEN = 1111, 16 Bits for the AD7920 burst mode (FSM = 1 in the serial port control register, SPC) with SLEN = 1101, 14 Bits for the AD7910 internal serial clock CLKX (MCM = 1 in SPC register) and internal To implement power-down mode, SLEN should be set to 0111 frame signal (TXM = 1 in the SPC), so both pins are configured as to issue an 8-bit SCLK burst. The connection diagram is shown outputs. For the AD7920, the word length should be set to 16 bits in Figure 26. The ADSP-218x has the TFS and RFS of the (FO = 0 in the SPC register). This DSP allows frames with a word SPORT tied together, with TFS set as an output and RFS set as length of 16 bits or 8 bits. Therefore, in the case of the AD7910 an input. The DSP operates in alternate framing mode and the where just 14 bits could be required, the FO bit would be set up to SPORT control register is set up as described. The frame 16 bits also. This means that to obtain the conversion result, 16 SCLKs are needed and two trailing zeros are clocked out in the two synchronization signal generated on the TFS is tied to CS and, last clock cycles. as with all signal processing applications, equidistant sampling is necessary. However, in this example, the timer interrupt is To summarize, the values in the SPC register are: used to control the sampling rate of the ADC and, under certain conditions, equidistant sampling can not be achieved. FO = 0 FSM = 1
AD7910/AD7920* ADSP-218x*
MCM = 1 TXM = 1
SCLK SCLK
The format bit, FO, can be set to 1 to set the word length to
SDATA DR
eight bits to implement the power-down mode on the AD7910/AD7920.
CS RFS
Figure 25 shows the connection diagram. It should be noted
TFS
that for signal processing applications, it is imperative that the
*ADDITIONAL PINS OMITTED FOR CLARITY
02976-026 frame synchronization signal from the TMS320C541 provides equidistant sampling. Figure 26. Interfacing to the ADSP-218x
AD7910/AD7920* TMS320C541*
The timer registers are loaded with a value that provides an interrupt at the required sample interval. When an interrupt is
SCLK CLKX
received, a value is transmitted with TFS/DT (ADC control word). The TFS is used to control the RFS and thus the reading
CLKR
of data. The frequency of the serial clock is set in the SCLKDIV
SDATA DR
register. When the instruction to transmit with TFS is given, that is, TX0 = AX0, the state of the SCLK is checked. The DSP
CS FSX
waits until the SCLK has gone high, low, and high before transmission starts. If the timer and SCLK values are chosen
FSR
such that the instruction to transmit occurs on or near the
*ADDITIONAL PINS OMITTED FOR CLARITY
rising edge of SCLK, the data can be transmitted or it can wait 02976-025 Figure 25. Interfacing to the TMS320C541 until the next clock edge. Rev. C | Page 20 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS AD7910 AD7920 TIMING SPECIFICATIONS TIMING EXAMPLES TIMING EXAMPLE 1 TIMING EXAMPLE 2 ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT DIGITAL INPUTS MODES OF OPERATION NORMAL MODE POWER-DOWN MODE POWER-UP TIME POWER VS. THROUGHPUT RATE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7910/AD7920 TO TMS320C541 INTERFACE AD7910/AD7920 TO ADSP-218x AD7910/AD7920 TO DSP563xx INTERFACE APPLICATION HINTS GROUNDING AND LAYOUT EVALUATING PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE