Datasheet AD7664 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | 16-Bit 570 kSPS CMOS Successive Approximation PulSAR ADC with No Missing Codes |
| Pages / Page | 25 / 6 — AD7664. PIN CONFIGURATION. ND G. AGND. 36 AGND. AVDD. 35 CNVST. 34 PD. … |
| Revision | F |
| File Format / Size | PDF / 564 Kb |
| Document Language | English |
AD7664. PIN CONFIGURATION. ND G. AGND. 36 AGND. AVDD. 35 CNVST. 34 PD. DGND. 33 RESET. OB/2C. 32 CS. WARP. 31 RD. IMPULSE. TOP VIEW. 30 DGND. SER/PAR
Model Line for this Datasheet
Text Version of Document
AD7664 PIN CONFIGURATION D ND G GN F F NC NC NC NC NC IN NC NC NC IN RE RE 8 7 6 5 4 3 2 1 0 9 8 7 4 4 4 4 4 4 4 4 4 3 3 3 AGND 1 36 AGND AVDD 2 35 CNVST NC 3 34 PD DGND 4 33 RESET OB/2C 5 32 CS WARP AD7664 6 31 RD IMPULSE TOP VIEW 7 30 DGND SER/PAR (Not to Scale) 8 29 BUSY D0 9 28 D15 D1 10 27 D14 D2 11 26 D13 D3 12 25 D12 3 4 5 6 7 8 9 0 1 2 3 4 1 1 1 1 1 1 1 2 2 2 2 2 T C K D D D K C R L IN UT L /IN D D D ND O C /S R OV DV DG DO VSYN VSC C OGN /S /SYN 0 ER /EXT D /S 1 4 D9 /IN /IN 8 D D D 5 6 /R D /R D D 7 1 D D1 NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EPAD IS CONNECTED TO GROUND; HOWEVER, THIS CONNECTION IS NOT REQUIRED TO MEET SPECIFIED PERFORMANCE. PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Type Description
1 AGND P Analog Power Ground Pin. 2 AVDD P Input Analog Power Pins. Nominally 5 V. 3, 40–42, NC No Connect. 44–48 4 DGND DI Must Be Tied to the Ground Where DVDD Is Referred. 5 OB/2C DI Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is straight binary; when LOW, the MSB is inverted resulting in a twos complement output from its internal shift register. 6 WARP DI Mode Selection. When HIGH and IMPULSE LOW, this input selects the fastest mode, the maximum throughput is achievable, and a minimum conversion rate must be applied in order to guarantee full specified accuracy. When LOW, full accuracy is maintained independent of the minimum conversion rate. 7 IMPULSE DI Mode Selection. When HIGH and WARP LOW, this input selects a reduced power mode. In this mode, the power dissipation is approximately proportional to the sampling rate. 8 SER/PAR DI Serial/Parallel Selection Input. When LOW, the Parallel Port is selected; when HIGH, the Serial Interface Mode is selected and some bits of the DATA bus are used as a Serial Port. 9–12 D[0:3] DO Bit 0 to Bit 3 of the Parallel Port Data Output Bus. These pins are always outputs, regardless of the state of SER/PAR. 13 D4 DI/O When SER/PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output Bus. or EXT/INT When SER/PAR is HIGH, this input, part of the Serial Port, is used as a digital select input for choosing the internal or an external data clock. With EXT/INT tied LOW, the internal clock is selected on the SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an external clock signal connected to the SCLK input. 14 D5 DI/O When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus. or INVSYNC When SER/PAR is HIGH, this input, part of the Serial Port, is used to select the active state of the SYNC signal. It is active in both Master and Slave Mode. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW. 15 D6 DI/O When SER/PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output Bus. or INVSCLK When SER/PAR is HIGH, this input, part of the Serial Port, is used to invert the SCLK signal. It is active in both Master and Slave Mode. REV. F –5– Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS DEFINITION OF SPECIFICATIONS Integral Nonlinearity Error (INL) Differential Nonlinearity Error (DNL) Full-Scale Error Unipolar Zero Error Spurious-Free Dynamic Range (SFDR) Effective Number of Bits (ENOB) Total Harmonic Distortion (THD) Signal-to-Noise Ratio (SNR) Signal to (Noise + Distortion) Ratio (S/[N+D]) Aperture Delay Transient Response Overvoltage Recovery Typical Performance Characteristics CIRCUIT INFORMATION CONVERTER OPERATION Modes of Operation Transfer Functions TYPICAL CONNECTION DIAGRAM Analog Input Driver Amplifier Choice Voltage Reference Input Power Supply POWER DISSIPATION VERSUS THROUGHPUT CONVERSION CONTROL DIGITAL INTERFACE PARALLEL INTERFACE SERIAL INTERFACE MASTER SERIAL INTERFACE Internal Clock SLAVE SERIAL INTERFACE External Clock External Discontinuous Clock Data Read after Conversion External Clock Data Read during Conversion MICROPROCESSOR INTERFACING SPI Interface (ADSP-219x) APPLICATION HINTS Bipolar and Wider Input Ranges Layout OUTLINE DIMENSIONS Revision History
1 AGND P Analog Power Ground Pin. 2 AVDD P Input Analog Power Pins. Nominally 5 V. 3, 40–42, NC No Connect. 44–48 4 DGND DI Must Be Tied to the Ground Where DVDD Is Referred. 5 OB/2C DI Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is straight binary; when LOW, the MSB is inverted resulting in a twos complement output from its internal shift register. 6 WARP DI Mode Selection. When HIGH and IMPULSE LOW, this input selects the fastest mode, the maximum throughput is achievable, and a minimum conversion rate must be applied in order to guarantee full specified accuracy. When LOW, full accuracy is maintained independent of the minimum conversion rate. 7 IMPULSE DI Mode Selection. When HIGH and WARP LOW, this input selects a reduced power mode. In this mode, the power dissipation is approximately proportional to the sampling rate. 8 SER/PAR DI Serial/Parallel Selection Input. When LOW, the Parallel Port is selected; when HIGH, the Serial Interface Mode is selected and some bits of the DATA bus are used as a Serial Port. 9–12 D[0:3] DO Bit 0 to Bit 3 of the Parallel Port Data Output Bus. These pins are always outputs, regardless of the state of SER/PAR. 13 D4 DI/O When SER/PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output Bus. or EXT/INT When SER/PAR is HIGH, this input, part of the Serial Port, is used as a digital select input for choosing the internal or an external data clock. With EXT/INT tied LOW, the internal clock is selected on the SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an external clock signal connected to the SCLK input. 14 D5 DI/O When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus. or INVSYNC When SER/PAR is HIGH, this input, part of the Serial Port, is used to select the active state of the SYNC signal. It is active in both Master and Slave Mode. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW. 15 D6 DI/O When SER/PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output Bus. or INVSCLK When SER/PAR is HIGH, this input, part of the Serial Port, is used to invert the SCLK signal. It is active in both Master and Slave Mode. REV. F –5– Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS DEFINITION OF SPECIFICATIONS Integral Nonlinearity Error (INL) Differential Nonlinearity Error (DNL) Full-Scale Error Unipolar Zero Error Spurious-Free Dynamic Range (SFDR) Effective Number of Bits (ENOB) Total Harmonic Distortion (THD) Signal-to-Noise Ratio (SNR) Signal to (Noise + Distortion) Ratio (S/[N+D]) Aperture Delay Transient Response Overvoltage Recovery Typical Performance Characteristics CIRCUIT INFORMATION CONVERTER OPERATION Modes of Operation Transfer Functions TYPICAL CONNECTION DIAGRAM Analog Input Driver Amplifier Choice Voltage Reference Input Power Supply POWER DISSIPATION VERSUS THROUGHPUT CONVERSION CONTROL DIGITAL INTERFACE PARALLEL INTERFACE SERIAL INTERFACE MASTER SERIAL INTERFACE Internal Clock SLAVE SERIAL INTERFACE External Clock External Discontinuous Clock Data Read after Conversion External Clock Data Read during Conversion MICROPROCESSOR INTERFACING SPI Interface (ADSP-219x) APPLICATION HINTS Bipolar and Wider Input Ranges Layout OUTLINE DIMENSIONS Revision History
