Datasheet AD7730, AD7730L (Analog Devices) - 14

AD7730/AD7730L Bit Bit Location Mnemonic Description
CR3 ZERO A zero
must
be written to this bit to ensure correct operation of the AD7730. CR2–CR0 RS2–RS0 Register Selection Bits. RS2 is the MSB of the three selection bits. The three bits select which register type the next read or write operation operates upon as shown in Table VIII.
Table VIII. Register Selection RS2 RS1 RS0 Register
0 0 0 Communications Register (Write Operation) 0 0 0 Status Register (Read Operation) 0 0 1 Data Register 0 1 0 Mode Register 0 1 1 Filter Register 1 0 0 DAC Register 1 0 1 Offset Register 1 1 0 Gain Register 1 1 1 Test Register
Status Register (RS2–RS0 = 0, 0, 0); Power-On/Reset Status: CX Hex
The Status Register is an 8-bit read-only register. To access the Status Register, the user must write to the Communications Register selecting either a single-shot read or continuous read mode and load bits RS2, RS1, RS0 with 0, 0, 0. Table IX outlines the bit desig- nations for the Status Register. SR0 through SR7 indicate the bit location, SR denoting the bits are in the Status Register. SR7 denotes the first bit of the data stream. Figure 5 shows a flowchart for reading from the registers on the AD7730. The number in brackets indicates the power-on/reset default status of that bit.
Table IX. Status Register
SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 RDY (1) STDY (1) STBY (0) NOREF (0) MS3 (X) MS2 (X) MS1 (X) MS0 (X)
Bit Bit Location Mnemonic Description
SR7 RDY Ready Bit. This bit provides the status of the RDY flag from the part. The status and function of this bit is the same as the RDY output pin. A number of events set the RDY bit high as indi- cated in Table XVIII. SR6 STDY Steady Bit. This bit is updated when the filter writes a result to the Data Register. If the filter is in FASTStep mode (see Filter Register section) and responding to a step input, the STDY bit remains high as the initial conversion results become available. The RDY output and bit are set low on these initial conversions to indicate that a result is available. If the STDY is high, however, it indicates that the result being provided is not from a fully settled second-stage FIR filter. When the FIR filter has fully settled, the STDY bit will go low coincident with RDY. If the part is never placed into its FASTStep mode, the STDY bit will go low at the first Data Register read and it is not cleared by subsequent Data Register reads. A number of events set the STDY bit high as indicated in Table XVIII. STDY is set high along with RDY by all events in the table except a Data Register read. SR5 STBY Standby Bit. This bit indicates whether the AD7730 is in its Standby Mode or normal mode of operation. The part can be placed in its standby mode using the STANDBY input pin or by writing 011 to the MD2 to MD0 bits of the Mode Register. The power-on/reset status of this bit is 0 assuming the STANDBY pin is high. SR4 NOREF No Reference Bit. If the voltage between the REF IN(+) and REF IN(–) pins is below 0.3 V, or either of these inputs is open-circuit, the NOREF bit goes to 1. If NOREF is active on comple- tion of a conversion, the Data Register is loaded with all 1s. If NOREF is active on completion of a calibration, updating of the calibration registers is inhibited. SR3–SR0 MS3–MS0 These bits are for factory use. The power-on/reset status of these bits vary, depending on the factory-assigned number. –14– REV. B