Datasheet AD7730, AD7730L (Analog Devices) - 6

AD7730/AD7730L DIFFERENTIAL PROGRAMMABLE PROGRAMMABLE GAIN BUFFER AMPLIFIER REFERENCE SIGMA DELTA ADC SIGMA-DELTA ADC DIGITAL FILTER AMPLIFIER THE BUFFER AMPLIFIER THE REFERENCE INPUT TO THE THE SIGMA-DELTA TWO STAGE FILTER THAT THE SIGMA DELTA PRESENTS A HIGH IMPEDANCE THE PROGRAMMABLE GAIN PART IS DIFFERENTIAL AND ARCHITECTURE ENSURES 24 BITS ALLOWS PROGRAMMING OF ARCHITECTURE ENSURES 24 BITS INPUT STAGE FOR THE ANALOG AMPLIFIER ALLOWS FOUR FACILITATES RATIOMETRIC NO MISSING CODES. THE OUTPUT UPDATE RATE AND NO MISSING CODES. THE INPUTS ALLOWING SIGNIFICANT UNIPOLAR AND FOUR BIPOLAR OPERATION. THE REFERENCE ENTIRE SIGMA-DELTA ADC CAN SETTLING TIME AND WHICH HAS ENTIRE SIGMA DELTA. ADC CAN EXTERNAL SOURCE INPUT RANGES FROM VOLTAGE CAN BE SELECTED TO BE CHOPPED TO REMOVE DRIFT A FAST STEP MODE BE CHOPPED TO REMOVE DRIFT IMPEDANCES +10mV TO +80mV BE NOMINALLY +2.5V OR +5V ERRORS (SEE FIGURE 3) ERRORS SEE PAGE 24 SEE PAGE 24 SEE PAGE 25 SEE PAGE 26 SEE PAGE 26 SEE PAGE BURNOUT CURRENTS TWO 100nA BURNOUT CURRENTS ALLOW THE USER TO EASILY DETECT IF A AV TRANSDUCER HAS BURNT DD DVDD REF IN(–) REF IN(+) STANDBY MODE OUT OR GONE OPEN-CIRCUIT THE STANDBY MODE REDUCES SEE PAGE 25 REFERENCE DETECT AD7730 POWER CONSUMPTION TO 5 A VBIAS AV SEE PAGE 33 DD AIN1(+) SIGMA-DELTA A/D CONVERTER STANDBY AIN1(–) SIGMA- PROGRAMMABLE SYNC CLOCK OSCILLATOR DELTA DIGITAL + CIRCUIT MUX PGA MODULATOR FILTER +/– THE CLOCK SOURCE FOR THE BUFFER PART CAN BE PROVIDED BY AN AIN2(+)/D1 MCLK IN EXTERNALLY-APPLIED CLOCK OR 6-BIT CLOCK BY CONNECTING A CRYSTAL OR AIN2(–)/D0 AGND DAC SERIAL INTERFACE GENERATION MCLK OUT CERAMIC RESONATOR ACROSS AND CONTROL LOGIC THE CLOCK PINS REGISTER BANK SEE PAGE 32 SCLK CS CALIBRATION ANALOG MULTIPLEXER MICROCONTROLLER DIN ACX AC A TWO-CHANNEL DIFFERENTIAL DOUT EXCITATION MULTIPLEXER SWITCHES ONE OF THE TWO DIFFERENTIAL INPUT ACX CLOCK CHANNELS TO THE BUFFER SERIAL INTERFACE AMPLIFIER. THE MULTIPLEXER IS CONTROLLED VIA THE SERIAL AGND DGND POL RDY RESET SPI*-COMPATIBLE OR DSP- INTERFACE COMPATIBLE SERIAL INTERFACE WHICH CAN BE OPERATED FROM SEE PAGE 24 JUST THREE WIRES. ALL FUNCTIONS ON THE PART CAN BE ACCESSED VIA THE SERIAL INTERFACE SEE PAGE 35 AC EXCITATION OUTPUT DRIVERS OFFSET/TARE DAC REGISTER BANK FOR AC-EXCITED BRIDGE THE SECOND ANALOG INPUT ALLOWS A PROGRAMMED THIRTEEN REGISTERS CONTROL APPLICATIONS, THE ACX CHANNEL CAN BE VOLTAGE TO BE EITHER ADDED ALL FUNCTIONS ON THE PART AND OUTPUTS PROVIDE SIGNALS RECONFIGURED TO BECOME TWO OR SUBTRACTED FROM THE PROVIDE STATUS INFORMATION THAT CAN BE USED TO SWITCH OUTPUT DIGITAL PORT LINES ANALOG INPUT SIGNAL BEFORE AND CONVERSION RESULTS THE POLARITY OF THE BRIDGE WHICH CAN BE PROGRAMMED IT IS APPLIED TO THE PGA EXCITATION VOLTAGE OVER THE SERIAL INTERFACE SEE PAGE 11 SEE PAGE 24 SEE PAGE 41 SEE PAGE 33 *SPI IS A TRADEMARK OF MOTOROLA, INC.
Figure 2. Detailed Functional Block Diagram –6– REV. B