Datasheet AD7819 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | +2.7 V to +5.5 V, 200 kSPS 8-Bit Sampling ADC |
| Pages / Page | 12 / 5 — AD7819. PIN FUNCTION DESCRIPTIONS. Pin No. Mnemonic. Description. PIN … |
| Revision | B |
| File Format / Size | PDF / 186 Kb |
| Document Language | English |
AD7819. PIN FUNCTION DESCRIPTIONS. Pin No. Mnemonic. Description. PIN CONFIGURATION. DIP/SOIC. REF. VDD. 15 DB7. GND 3. 14 DB6. CONVST 4. 13 DB5
Model Line for this Datasheet
Text Version of Document
AD7819 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description
1 VREF Reference Input, 1.2 V to VDD. 2 VIN Analog Input, 0 V to VREF. 3 GND Analog and Digital Ground. 4 CONVST Convert Start. A low-to-high transition on this pin initiates a 1.5 µs pulse on an internally generated CONVST signal. A high-to-low transition on this line initiates the conversion process if the internal CONVST signal is low. Depending on the signal on this pin at the end of a conversion, the AD7819 automatically powers down. 5 CS Chip Select. This is a logic input. CS is used in conjunction with RD to enable outputs. 6 RD Read Pin. This is a logic input. When CS is low and RD goes low, the DB7–DB0 leave their high impedance state and data is driven onto the data bus. 7 BUSY ADC Busy Signal. This is a logic output. This signal goes logic high during the conversion process. 8–15 DB0–DB7 Data Bit 0 to 7. These outputs are three-state TTL-compatible. 16 VDD Positive power supply voltage, 2.7 V to 5.5 V.
PIN CONFIGURATION DIP/SOIC V 1 16 REF VDD V 2 15 DB7 IN GND 3 14 DB6 AD7819 CONVST 4 13 DB5 TOP VIEW CS 5 12 DB4 (Not to Scale) RD 6 11 DB3 BUSY 7 10 DB2 DB0 8 9 DB1
–4– REV. B
1 VREF Reference Input, 1.2 V to VDD. 2 VIN Analog Input, 0 V to VREF. 3 GND Analog and Digital Ground. 4 CONVST Convert Start. A low-to-high transition on this pin initiates a 1.5 µs pulse on an internally generated CONVST signal. A high-to-low transition on this line initiates the conversion process if the internal CONVST signal is low. Depending on the signal on this pin at the end of a conversion, the AD7819 automatically powers down. 5 CS Chip Select. This is a logic input. CS is used in conjunction with RD to enable outputs. 6 RD Read Pin. This is a logic input. When CS is low and RD goes low, the DB7–DB0 leave their high impedance state and data is driven onto the data bus. 7 BUSY ADC Busy Signal. This is a logic output. This signal goes logic high during the conversion process. 8–15 DB0–DB7 Data Bit 0 to 7. These outputs are three-state TTL-compatible. 16 VDD Positive power supply voltage, 2.7 V to 5.5 V.
PIN CONFIGURATION DIP/SOIC V 1 16 REF VDD V 2 15 DB7 IN GND 3 14 DB6 AD7819 CONVST 4 13 DB5 TOP VIEW CS 5 12 DB4 (Not to Scale) RD 6 11 DB3 BUSY 7 10 DB2 DB0 8 9 DB1
–4– REV. B
