Datasheet AD7819 (Analog Devices) - 9

AD7819 Typical Performance Characteristics
external CONVST and this internal CONVST are input to an OR gate. The resultant signal has the duration of the longer of the two input signals. Once a conversion has been initiated, the
10
BUSY signal goes high to indicate a conversion is in progress. At the end of conversion the sampling circuit returns to its track- ing mode. The end of conversion is indicated by the BUSY signal going low. This signal may be used to initiate an ISR on a
1
microprocessor. At this point the conversion result is latched
mW
into the output register where it may be read. The AD7819 has
–
an 8-bit wide parallel interface. The state of the external CONVST signal at the end of conversion also establishes the mode of
POWER 0.1
operation of the AD7819.
Mode 1 Operation (High Speed Sampling)
If the external CONVST is logic high when BUSY goes low, the part is said to be in Mode 1 operation. While operating in Mode
0.01
1 the AD7819 will not power down between conversions. The
0 5 10 15 20 25 30 35 40 45 50 THROUGHPUT – kSPS
AD7819 should be operated in Mode 1 for high speed sam- pling applications, i.e., throughputs greater than 100 kSPS. Figure 10. Power vs. Throughput Figure 13 shows the timing for Mode 1 operation. From this diagram one can see that a minimum delay of the sum of the
0
conversion time and read time must be left between two succes-
AD7819 –10 2048 POINT FFT
sive falling edges of the external CONVST. This is to ensure that
SAMPLING 136.054kHz –20 F
a conversion is not initiated during a read.
IN = 29.961kHz –30 Mode 2 Operation (Automatic Power-Down) –40
At slower throughput rates the AD7819 may be powered down between conversion to give a superior power performance.
–50 dBs
This is Mode 2 Operation and it is achieved by bringing the
–60
CONVST signal logic low before the falling edge of BUSY. Fig-
–70
ure 14 shows the timing for Mode 2 Operation. The falling edge
–80
of the external CONVST signal may occur before or after the falling edge of the internal CONVST signal, but it is the later
–90
occurring falling edge of both that controls when the first conver-
–100
sion will take place. If the falling edge of the external CONVST
0 7 13 20 27 33 40 47 53 60 66 FREQUENCY – kHz
occurs after that of the internal CONVST, it means that the Figure 11. SNR moment of the first conversion is controlled exactly, regardless of any jitter associated with the internal CONVST signal. The
TIMING AND CONTROL
parallel interface is still fully operational while the AD7819 is The AD7819 has only one input for timing and control, i.e., powered down. The AD7819 is powered up again on the rising the CONVST (convert start signal). The rising edge of this edge of the CONVST signal. The gated CONVST pulse will CONVST signal initiates a 1.5 µs pulse on an internally gener- now remain high long enough for the AD7819 to fully power ated CONVST signal. This pulse is present to ensure the part up, which takes about 1.5 µs. This is ensured by the internal has enough time to power up before a conversion is initiated. If CONVST signal, which will remain high for 1.5 µs. the external CONVST signal is low, the falling edge of the in- ternal CONVST signal will cause the sampling circuit to go into hold mode and initiate a conversion. If, however, the external
CONVST EXT
CONVST signal is high when the internal CONVST goes low,
(PIN 4) GATED
it is upon the falling edge of the external CONVST signal that
INT
the sampling circuitry will go into hold mode and initiate a conversion. The use of the internally generated 1.5 µs pulse as
1.5 s
previously described can be likened to the configuration shown Figure 12. in Figure 12. The application of a CONVST signal at the CONVST pin triggers the generation of a 1.5 µs pulse. Both the –8– REV. B