Datasheet AD9243 (Analog Devices) - 22

ManufacturerAnalog Devices
DescriptionComplete 14-Bit, 3 MSPS Monolithic A/D Converter
Pages / Page25 / 22 — AD9243. VINA2. VINB2. 1N5711. TP10. TP11. TP12. TP13. TP14. TP15. TP16. …
RevisionA
File Format / SizePDF / 436 Kb
Document LanguageEnglish

AD9243. VINA2. VINB2. 1N5711. TP10. TP11. TP12. TP13. TP14. TP15. TP16. TP3. TP4. TP5. TP17. TP6. TP7. TP8. TP9. +5VA. R20. R21. R22. R23. R24. R25. R26. R27. R28. R29. R30. R31. R32

AD9243 VINA2 VINB2 1N5711 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP3 TP4 TP5 TP17 TP6 TP7 TP8 TP9 +5VA R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32

Model Line for this Datasheet

Text Version of Document

AD9243 VINA2 VINB2 8 J8 J8 J8 J8 J8 J8 J8 J8 J8 J8 J8 J8 J8 J8 13 11 9 7J 5 3 1 33 27 25 23 21 19 17 15 D1 1N5711 D3 1N5711 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP3 TP4 TP5 TP17 TP6 TP7 TP8 TP9 D4 1N5711
V V V V V V V V V V V V V V V
D2 1N5711 +5VA A +5VA A R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 J8 22.1 22.1 22.1 22.1 22.1 22.1 22.1 22.1 22.1 22.1 22.1 22.1 22.1 22.1 22.1
V V
R12 40 33 AC COUPLE OPTION R15 33 R39 JP17 JP18 A A TP26 SJ6 F
m
F 6
m
C19 0.1 C21 0.1 F F
m m
F CC 7 4 EE
m
V V +DRVDD C24 0.1 +DRVDD C25 0.1 C22 0.1 AD845 D U5 11 12 13 14 15 16 17 18 20 11 12 13 14 15 16 17 18 20 U4 2 3 CW +5V TPD Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
V
DECOUPLING +5VD A +5VD
m
F U6 U7 R11 500 BUFFER C18 0.1 6 4 A
V
G1 G2 A7 A6 A5 A4 A3 A2 A1 A0 GND 74HC541N G1 G2 A7 A6 A5 A4 A3 A2 A1 A0 GND 74HC541N R14 74HC04 10k U5 U5 U5 2 1 2 A 10 1 12 3 19 10 19
m
F 5 C17 10 16V D7 9 D8 8 D9 7 D10 6 D11 5 D12 4 D13 3 D0 8 D1 7 D2 6 D3 5 D4 4 D5 3 F CLK 9
V m
Q1 2N2222 SPARE GATES C20 F R10 A 500 0.1
m
C26 0.1 TP25
V
A C38 JP24
V
U8 R8 316 A R13 +5VA 10k R40 R41 JP23 DECOUPLING JP15 CLKB JP16 CLK
m
F
V
AC COUPLE OPTION 3 2 1 C16 R7 1k 0.1 DIRECT COUPLE OPTION A B 12
V V
10 12 CW JP14 JP13 R16 5k R18 5k A
V
A 2 U5 U5 U8 A A U8 U8 74HC14 13 98
m
F +5VA R6 820
V V
11 34 C23
m
F R9 U8 U8 13 R17 6
m
F 0.1 1k A C14 C15 50 98 1 10 +5VA 0.1 0.1 J1 A U8
V
U5 R19 50 A CC 7 4 EE V V 65 VIN 11 TP2 AD817 TPD TPC U3 3 2 A J9 ADC_CLK CLK D13
m
F V C13 10 16 ADC CLKIN A VINA1 VINB1 TPC TPD CML
V
R4 50
V V
R37 33 R38 33 JP21 JP22 JP1 TP24 +5VD
V
C36 15pF A C37 15pF
V
A A +5VA R3 15k R36 200 25 24 D13 23 D12 22 D11 21 D10 20 D9 19 D8 18 D7 17 D6 16 D5 15 D4 14 D3 13 D2 12 D1 11 D0 7
m
F A F EXTERNAL REFERENCE DRIVE
V
C42 0.1 JP8
m
C A AVSS1 OTR BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7 BIT8 BIT9 CLK JP10 R5 10k A E 29 BIT10 BIT11 BIT12 BIT13 BIT14 C11 0.1 6 S 5 4 DVDD F 6
m
JP7 C8 AVSS2 0.1 DRVDD T1 8 8 8 8 OUT 42 63 A J8 J J J8 J J8 J8 J8 J J8 J8 J8 AVDD1 U1 V F 4
m
U2 DVSS C10 GND 26 39 28 29 30 31 32 34 35 36 37 38 REF43 0.1 IN F AVDD2 28 1 2 3
m
AD9243MQFP 1 V DRVSS NC NC NC C9 PRI 2 0.1 5 A F VREF SENSE REFCOM CAPT CAPB CML VINA VINB F 8
m m
J8 J8 J8 J8 J8 J8 J8 J8 J8 J8 J8 A C43
V
C12 0.1 2 4J 6 8 32 31 33 37 36 39 41 42 0.1 A 10 12 14 16 18 20 22 24 A R35 50 F
m
A J10 C2 0.1 CC AIN V F +DRVDD F A
m m
C1 10 16V C6 0.1 + 5 SETS OF PADS TO CONNECT GROUNDS F A
m
CC EE 1 +5VA +5VD V V +DRVDD JP6 C5 10 16V B F F F F F SJ5 +
m m m m m
JP3 JP4 JP5 F F C32 0.1 SJ4 A C33 0.1 A C34 0.1 A C35 0.1 A C40 0.1 A
m m
JP11 TP1 C3 C4 F A
m
32 1 SJ3 +5VA 0.1 0.1 B A C7 0.1 L1 L2 SJ2 L3 L4 L5 R1
V
A R2
V
A JP12 F F F F F SJ1 10k
m
10k A
m m m m
32 C28 22 25V C29 22 25V A A C30 22 25V A C31 22 25V A C39 22 25V F JG1-WIRE ETCH CKT SIDE JG1
m
+ + + + + C41 JP2 0.1 TP18 TP19 TP20 TP21 TP27 TP22 TP23 J2 J3 J4 J5 +3 J11 J6 J7 CC EE TPC TPD CML +5A +5D OR –V VINA2 VINA1 VINB2 VINB1 +V +5 DGND AGND
Figure 51. Evaluation Board Schematic REV. A –21–