Datasheet AD7701 (Analog Devices) - 8

ManufacturerAnalog Devices
Description16-Bit Sigma-Delta ADC
Pages / Page21 / 8 — AD7701. IOL. 1.6mA. CAL. OUTPUT. +2.1V. CLKIN. PIN. 100pF. IOH. SC1, SC2. …
RevisionE
File Format / SizePDF / 321 Kb
Document LanguageEnglish

AD7701. IOL. 1.6mA. CAL. OUTPUT. +2.1V. CLKIN. PIN. 100pF. IOH. SC1, SC2. SC1, SC2 VALID. 200µA. SLEEP. DRDY. t12. t11. SCLK. t15. t13. t16. HI-Z. DATA. SDATA. VALID

AD7701 IOL 1.6mA CAL OUTPUT +2.1V CLKIN PIN 100pF IOH SC1, SC2 SC1, SC2 VALID 200µA SLEEP DRDY t12 t11 SCLK t15 t13 t16 HI-Z DATA SDATA VALID

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AD7701 IOL 1.6mA TO CAL OUTPUT +2.1V CLKIN PIN CL t1 t2 t 100pF 3 IOH SC1, SC2 SC1, SC2 VALID 200µA SLEEP
Figure 1. Load Circuit for Access Figure 2a. Calibration Control Timing Figure 2b. SLEEP Mode Timing Time and Bus Relinquish Time
DRDY CS t12 CS t11 CS SCLK t15 t13 t16 t t 10 HI-Z 14 DATA SDATA HI-Z HI-Z HI-Z VALID SDATA DB15 DB14 DB1 DB0 DATA SDATA VALID
Figure 3. SSC Mode Data Figure 4a. SEC Mode Data Hold Time Figure 4b. SEC Mode Timing Diagram Hold Time
CLKIN CS DRDY t7 CS t8 HI-Z t SCLK 17 t SCLK 4 t5 t t t 6 18 19 t START 5 HI-Z HI-Z HI-Z HI-Z SDATA DB8 DB9 DB7 STOP 1 STOP 2 SDATA DB15 DB14 DB1 DB0 HIGH BYTE LOW BYTE
Figure 5. SSC Mode Timing Diagram Figure 6. AC Mode Timing Diagram
DEFINITION OF TERMS Bipolar Zero Error Linearity Error
This is the deviation of the midscale transition (0111 . 111 to This is the maximum deviation of any code from a straight line 1000 . 000) from the ideal (AGND – 0.5 LSB) when operating passing through the endpoints of the transfer function. The in the Bipolar mode. It is expressed in microvolts. endpoints of the transfer function are zero scale (not to be
Bipolar Negative Full-Scale Error
confused with bipolar zero), a point 0.5 LSB below the first This is the deviation of the first code transition from the ideal code transition (000 . 000 to 000 . 001) and full scale, a (–V point 1.5 LSB above the last code transition (111 . 110 to REF + 0.5 LSB) when operating in the Bipolar mode. It is expressed in microvolts. 111 . 111). The error is expressed as a percentage of full scale.
Positive Full-Scale Overrange Differential Linearity Error
Positive full-scale overrange is the amount of overhead available This is the difference between any code’s actual width and the to handle input voltages greater than +V ideal (1 LSB) width. Differential linearity error is expressed in REF (for example, noise peaks or excess voltages due to system gain errors in system LSBs. A differential linearity specification of ± 1 LSB or less calibration routines) without introducing errors due to overloading guarantees monotonicity. the analog modulator or overflowing the digital filter. It is
Positive Full-Scale Error
expressed in millivolts. Positive full-scale error is the deviation of the last code transition
Negative Full-Scale Overrange
(111 . 110 to 111 . 111) from the ideal (VREF ± 3/2 LSBs). This is the amount of overhead available to handle voltages below It applies to both positive and negative analog input ranges and –V is expressed in microvolts. REF without overloading the analog modulator or overflowing the digital filter. Note that the analog input will accept negative
Unipolar Offset Error
voltage peaks even in the Unipolar mode. The overhead is Unipolar offset error is the deviation of the first code transition expressed in millivolts. from the ideal (AGND + 0.5 LSB) when operating in the Uni- polar mode. It is expressed in microvolts. REV. E –7– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATIONS PIN FUNCTION DESCRIPTIONS TIMING CHARACTERISTICS DEFINITION OF TERMS Linearity Error Differential Linearity Error Positive Full-Scale Error Unipolar Offset Error Bipolar Zero Error Bipolar Negative Full-Scale Error Positive Full-Scale Overrange Negative Full-Scale Overrange Offset Calibration Range Full-Scale Calibration Range Input Span GENERAL DESCRIPTION THEORY OF OPERATION DIGITAL FILTERING FILTER CHARACTERISTICS USING THE AD7701 SYSTEM DESIGN CONSIDERATIONS CLOCKING ANALOG INPUT RANGES INPUT SIGNAL CONDITIONING Source Resistance Antialias Considerations VOLTAGE REFERENCE CONNECTIONS GROUNDING AND SUPPLY DECOUPLING ACCURACY AND AUTOCALIBRATION CALIBRATION RANGE POWER-UP AND CALIBRATION POWER SUPPLY SEQUENCING GROUNDING SINGLE-SUPPLY OPERATION SLEEP MODE DIGITAL INTERFACE Synchronous Self-Clocking Mode (SSC) Synchronous External Clock Mode (SEC) Asynchronous Communications (AC) Mode DIGITAL NOISE AND OUTPUT LOADING OUTLINE DIMENSIONS Revision History
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