link to page 20 link to page 20 Data SheetAD8139THEORY OF OPERATION The AD8139 is a high speed, low noise differential amplifier outputs of identical amplitude and exactly 180° out of phase. The fabricated on the Analog Devices second-generation extra fast output balance performance does not require tightly matched complementary bipolar (XFCB) process. It is designed to external components, nor does it require that the feedback factors provide two closely balanced differential outputs in response of each loop be equal to each other. Low frequency output balance to either differential or single-ended input signals. Differential is limited ultimately by the mismatch of an on-chip voltage divider, gain is set by external resistors, similar to traditional voltage- which is trimmed for optimum performance. feedback operational amplifiers. The common-mode level of Output balance is measured by placing a well-matched resistor the output voltage is set by a voltage at the VOCM pin and is divider across the differential voltage outputs and comparing independent of the input common-mode voltage. The AD8139 the signal at the midpoint of the divider with the magnitude of has an H-bridge input stage for high slew rate, low noise, and the differential output. By this definition, output balance is low distortion operation and rail-to-rail output stages that equal to the magnitude of the change in output common-mode provide maximum dynamic output range. This set of features voltage divided by the magnitude of the change in output allows for convenient single-ended-to-differential conversion, differential-mode voltage: a common need to take advantage of modern high resolution ADCs with differential inputs. Δ O, V cm Output Balance (3) TYPICAL CONNECTION AND DEFINITION OF V Δ O, dm TERMS The block diagram of the AD8139 in Figure 60 shows the Figure 59 shows a typical connection for the AD8139, using external differential feedback loop (RF/RG networks and the matched external RF/RG networks. The differential input terminals differential input transconductance amplifier, GDIFF) and the of the AD8139, VAP and VAN, are used as summing junctions. internal common-mode feedback loop (voltage divider across An external reference voltage applied to the VOCM terminal sets VOP and VON and the common-mode input transconductance the output common-mode voltage. The two output terminals, amplifier, GCM). The differential negative feedback drives the VOP and VON, move in opposite directions in a balanced fashion voltages at the summing junctions VAN and VAP to be essentially in response to an input signal. equal to each other. CF VAN = VAP (4) The common-mode feedback loop drives the output common- RFR mode voltage, sampled at the midpoint of the two 500 Ω resistors, GVAPVONVIP+– to equal the voltage set at the VOCM terminal. This ensures that VOCMAD8139RVL, dmO, dmR V GVANV O, dm V IN–OP+ OP V OCM V (5) 2 RF and 50 0 V 9- C O, dm F 467 V V (6) 0 ON OCM 2 Figure 59. Typical Connection RGRF The differential output voltage is defined as VIN10pF VO, dm = VOP − VON (1) + Common-mode voltage is the average of two voltages. The GOVOP output common-mode voltage is defined as 500ΩMIDSUPPLYVAN GDIFFGCM500Ω OP V ON V VVAPOCM O, V cm (2) 2 Output BalanceGOVON+ Output balance is a measure of how well VOP and VON are matched in amplitude and how precisely they are 180° out of 10pF 1 V 05 IP 9- phase with each other. It is the internal common-mode feedback RGRF 67 04 loop that forces the signal component of the output common-mode Figure 60. Block Diagram towards zero, resulting in the near perfectly balanced differential Rev. C | Page 19 of 26 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAMS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS VS = ±5 V, VOCM = 0 V VS = 5 V, VOCM = 2.5 V ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Maximum Power Dissipation ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS THEORY OF OPERATION TYPICAL CONNECTION AND DEFINITION OF TERMS Output Balance APPLICATIONS INFORMATION ESTIMATING NOISE, GAIN, AND BANDWIDTH WITH MATCHED FEEDBACK NETWORKS Estimating Output Noise Voltage Voltage Gain Feedback Factor Notation Input Common-Mode Voltage Calculating Input Impedance Input Common-Mode Swing Considerations Bandwidth vs. Closed-Loop Gain Estimating DC Errors Other Impact of Mismatches in the Feedback Networks Driving a Capacitive Load Layout Considerations Terminating a Single-Ended Input Exposed Paddle (EP) OUTLINE DIMENSIONS ORDERING GUIDE